--- /dev/null
+/** @file\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ \r\r
+ This program and the accompanying materials are licensed and made available under\r\r
+ the terms and conditions of the BSD License that accompanies this distribution. \r\r
+ The full text of the license may be found at \r\r
+ http://opensource.org/licenses/bsd-license.php. \r\r
+ \r\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
+ \r\r
+\r
+**/\r
+\r
+#ifndef _FIRMWARE_UPDATE_H_\r
+#define _FIRMWARE_UPDATE_H_\r
+\r
+#include <Uefi.h>\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Guid/FileInfo.h>\r
+\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+#include <Protocol/LoadedImage.h>\r
+#include <Protocol/SimpleFileSystem.h>\r
+#include <Protocol/Spi.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/FileHandleLib.h>\r
+#include <Library/HiiLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/ShellLib.h>\r
+#include <Library/UefiApplicationEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+\r
+//\r
+// Function Prototypes.\r
+//\r
+STATIC\r
+EFI_STATUS\r
+ReadFileData (\r
+ IN CHAR16 *FileName,\r
+ OUT UINT8 **Buffer,\r
+ OUT UINT32 *BufferSize\r
+ );\r
+\r
+STATIC\r
+EFI_STATUS\r
+InternalEraseBlock (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress\r
+ );\r
+\r
+#if 0\r
+STATIC\r
+EFI_STATUS\r
+InternalReadBlock (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ OUT VOID *ReadBuffer\r
+ );\r
+#endif\r
+\r
+STATIC\r
+EFI_STATUS\r
+InternalCompareBlock (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT8 *Buffer\r
+ );\r
+\r
+STATIC\r
+EFI_STATUS\r
+InternalWriteBlock (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT8 *Buffer,\r
+ IN UINT32 BufferSize\r
+ );\r
+\r
+STATIC\r
+VOID\r
+PrintHelpInfo (\r
+ VOID\r
+ );\r
+\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+SpiFlashRead (\r
+ IN UINTN Address,\r
+ IN OUT UINT32 *NumBytes,\r
+ OUT UINT8 *Buffer\r
+ );\r
+\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+SpiFlashWrite (\r
+ IN UINTN Address,\r
+ IN OUT UINT32 *NumBytes,\r
+ IN UINT8 *Buffer\r
+ );\r
+\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+SpiFlashBlockErase (\r
+ IN UINTN Address,\r
+ IN UINTN *NumBytes\r
+ );\r
+\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+ConvertMac (\r
+ CHAR16 *Str\r
+ );\r
+\r
+EFI_STATUS\r
+InitializeFVUPDATE (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ );\r
+\r
+//\r
+// Flash specific definitions.\r
+// - Should we use a PCD for this information?\r
+//\r
+#define BLOCK_SIZE SIZE_4KB\r
+\r
+//\r
+// Flash region layout and update information.\r
+//\r
+typedef struct {\r
+ EFI_PHYSICAL_ADDRESS Base;\r
+ UINTN Size;\r
+ BOOLEAN Update;\r
+} FV_REGION_INFO;\r
+\r
+//\r
+// MAC Address information.\r
+//\r
+#define MAC_ADD_STR_LEN 12\r
+#define MAC_ADD_STR_SIZE (MAC_ADD_STR_LEN + 1)\r
+#define MAC_ADD_BYTE_COUNT 6\r
+#define MAC_ADD_TMP_STR_LEN 2\r
+#define MAC_ADD_TMP_STR_SIZE (MAC_ADD_TMP_STR_LEN + 1)\r
+\r
+//\r
+// Command Line Data.\r
+//\r
+#define INPUT_STRING_LEN 255\r
+#define INPUT_STRING_SIZE (INPUT_STRING_LEN + 1)\r
+typedef struct {\r
+ BOOLEAN UpdateFromFile;\r
+ CHAR16 FileName[INPUT_STRING_SIZE];\r
+ BOOLEAN UpdateMac;\r
+ UINT8 MacValue[MAC_ADD_BYTE_COUNT];\r
+ BOOLEAN FullFlashUpdate;\r
+} FV_INPUT_DATA;\r
+\r
+//\r
+// Prefix Opcode Index on the host SPI controller.\r
+//\r
+typedef enum {\r
+ SPI_WREN, // Prefix Opcode 0: Write Enable.\r
+ SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register.\r
+} PREFIX_OPCODE_INDEX;\r
+\r
+//\r
+// Opcode Menu Index on the host SPI controller.\r
+//\r
+typedef enum {\r
+ SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address.\r
+ SPI_READ, // Opcode 1: READ, Read cycle with address.\r
+ SPI_RDSR, // Opcode 2: Read Status Register, No address.\r
+ SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address.\r
+ SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address.\r
+ SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address.\r
+ SPI_PROG, // Opcode 6: Byte Program, Write cycle with address.\r
+ SPI_WRSR, // Opcode 7: Write Status Register, No address.\r
+} SPI_OPCODE_INDEX;\r
+\r
+#endif\r