edk2: Remove packages moved to edk2-platforms

[mirror_edk2.git] / Vlv2TbltDevicePkg / Include / Platform.h

diff --git a/Vlv2TbltDevicePkg/Include/Platform.h b/Vlv2TbltDevicePkg/Include/Platform.h
deleted file mode 100644 (file)
index 4d1932f..0000000
--- a/Vlv2TbltDevicePkg/Include/Platform.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*++\r
-\r
-  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
-                                                                                   \r\r
-  SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-                                                                                   \r\r
-\r
-\r
-Module Name:\r
-\r
-  Platform.h\r
-\r
-Abstract:\r
-\r
-  Pinetrail platform specific information.\r
-\r
-**/\r
-\r
-#ifndef _PLATFORM_H\r
-#define _PLATFORM_H\r
-\r
-#include "ChipsetAccess.h"\r
-#include "PlatformBaseAddresses.h"\r
-\r
-\r
-//\r
-// Number of P & T states supported.\r
-//\r
-#define NPTM_P_STATES_SUPPORTED         16\r
-#define NPTM_T_STATES_SUPPORTED         8\r
-\r
-//\r
-// I/O APIC IDs, the code uses math to generate the numbers\r
-// instead of using these defines.\r
-//\r
-#define ICH_IOAPIC                     (1 << 0)\r
-#define ICH_IOAPIC_ID                   0x08\r
-\r
-//\r
-// Possible SMBus addresses that will be present.\r
-//\r
-#define SMBUS_ADDR_CH_A_1     0xA0\r
-#define SMBUS_ADDR_CH_A_2     0xA2\r
-#define SMBUS_ADDR_CH_B_1     0xA4\r
-#define SMBUS_ADDR_CH_B_2     0xA6\r
-#define SMBUS_ADDR_CH_C_1     0xA8\r
-#define SMBUS_ADDR_CH_C_2     0xAA\r
-#define SMBUS_ADDR_CH_D_1     0xAC\r
-#define SMBUS_ADDR_CH_D_2     0xAE\r
-#define SMBUS_ADDR_HOST_CLK_BUFFER  0xDC\r
-#define SMBUS_ADDR_ICH_SLAVE        0x44\r
-#define SMBUS_ADDR_HECETA     0x5C\r
-#define SMBUS_ADDR_SMBARP     0xC2\r
-#define SMBUS_ADDR_82573E     0xC6\r
-#define SMBUS_ADDR_CLKCHIP    0xD2\r
-#define SMBUS_ADDR_BRD_REV          0x4E\r
-#define SMBUS_ADDR_DB803            0x82\r
-\r
-//\r
-// SMBus addresses that used on this platform.\r
-//\r
-#define PLATFORM_SMBUS_RSVD_ADDRESSES { \\r
-  SMBUS_ADDR_CH_A_1, \\r
-  SMBUS_ADDR_CH_A_2, \\r
-  SMBUS_ADDR_HOST_CLK_BUFFER, \\r
-  SMBUS_ADDR_ICH_SLAVE, \\r
-  SMBUS_ADDR_SMBARP, \\r
-  SMBUS_ADDR_CLKCHIP, \\r
-  SMBUS_ADDR_BRD_REV, \\r
-  SMBUS_ADDR_DB803 \\r
-  }\r
-\r
-//\r
-// Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.\r
-//\r
-#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8\r
-\r
-//\r
-// CMOS usage\r
-//\r
-#define CMOS_CPU_BSP_SELECT         0x10\r
-#define CMOS_CPU_UP_MODE            0x11\r
-#define CMOS_CPU_RATIO_OFFSET       0x12\r
-#define CMOS_CPU_CORE_HT_OFFSET     0x13\r
-#define CMOS_EFI_DEBUG              0x14\r
-#define CMOS_CPU_BIST_OFFSET        0x15\r
-#define CMOS_CPU_VMX_OFFSET         0x16\r
-#define CMOS_ICH_PORT80_OFFSET      0x17\r
-#define CMOS_PLATFORM_DESIGNATOR    0x18      // Second bank CMOS location of Platform ID.\r
-#define CMOS_VALIDATION_TEST_BYTE   0x19      // BIT0 - Validation mailbox for UPonDP.\r
-#define CMOS_SERIAL_BAUD_RATE       0x1A      // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600\r
-#define CMOS_DCU_MODE_OFFSET        0x1B\r
-#define CMOS_VR11_SET_OFFSET        0x1C\r
-#define CMOS_SBSP_TO_AP_COMM        0x20      // SEC code use ONLY!!!\r
-#define CMOS_RESET_TYPE_BY_OS       0x52\r
-#define TCG_CMOS_MOR_AREA_OFFSET    0x65      // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &\r
-#define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E\r
-#define ACPI_TPM_REQUEST            0x75\r
-#define ACPI_TPM_LAST_REQUEST       0x76\r
-#define CMOS_BOOT_FLAG_ADDRESS      0x7E\r
-\r
-//\r
-// GPIO Index Data Structure.\r
-//\r
-typedef struct {\r
-  UINT8   Register;\r
-  UINT32  Value;\r
-} ICH_GPIO_DEV;\r
-\r
-//\r
-// CPU Equates\r
-//\r
-#define MAX_THREAD                      2\r
-#define MAX_CORE                        1\r
-#define MAX_DIE                         2\r
-#define MAX_CPU_SOCKET                  1\r
-#define MAX_CPU_NUM                     (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)\r
-\r
-#define MEM64_LEN                       0x00100000000\r
-#define RES_MEM64_36_BASE               0x01000000000 - MEM64_LEN   // 2^36\r
-#define RES_MEM64_36_LIMIT              0x01000000000 - 1           // 2^36\r
-#define RES_MEM64_39_BASE               0x08000000000 - MEM64_LEN   // 2^39\r
-#define RES_MEM64_39_LIMIT              0x08000000000 - 1           // 2^39\r
-#define RES_MEM64_40_BASE               0x10000000000 - MEM64_LEN   // 2^40\r
-#define RES_MEM64_40_LIMIT              0x10000000000 - 1           // 2^40\r
-\r
-#define PLATFORM_MAX_BUS_NUM             0x3f\r
-#define V_DEFAULT_SUBSYSTEM_DEVICE_ID    0x574d\r
-#define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b\r
-#define V_DEFAULT_SUBSYSTEM_VENDOR_ID    0x8086\r
-\r
-#endif\r