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[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / CpuIA32Lib / IA32 / CpuIA32.S

diff --git a/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S
new file mode 100644 (file)
index 0000000..b0c5b28
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S
@@ -0,0 +1,228 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#Module Name:\r
+#\r
+#  CpuIA32.c\r
+#\r
+#Abstract:\r
+#\r
+#--*/\r
+\r
+##include "CpuIA32.h"\r
+#include "EfiBind.h"\r
+\r
+#---------------------------------------------------------------------------\r
+    .586p:\r
+    #.MODEL flat,C\r
+    .code:\r
+\r
+#---------------------------------------------------------------------------\r
+\r
+.globl ASM_PFX(EfiHalt)\r
+.globl ASM_PFX(EfiWbinvd)\r
+.globl ASM_PFX(EfiInvd)\r
+.globl ASM_PFX(EfiCpuid)\r
+.globl ASM_PFX(EfiReadMsr)\r
+.globl ASM_PFX(EfiWriteMsr)\r
+.globl ASM_PFX(EfiReadTsc)\r
+.globl ASM_PFX(EfiDisableCache)\r
+.globl ASM_PFX(EfiEnableCache)\r
+.globl ASM_PFX(EfiGetEflags)\r
+.globl ASM_PFX(EfiDisableInterrupts)\r
+.globl ASM_PFX(EfiEnableInterrupts)\r
+.globl ASM_PFX(EfiCpuidExt)\r
+\r
+\r
+#VOID\r
+#EfiHalt (\r
+#  VOID\r
+#)\r
+ASM_PFX(EfiHalt):\r
+    hlt\r
+    ret\r
+#EfiHalt ENDP\r
+\r
+#VOID\r
+#EfiWbinvd (\r
+#  VOID\r
+#)\r
+ASM_PFX(EfiWbinvd):\r
+    wbinvd\r
+    ret\r
+#EfiWbinvd ENDP\r
+\r
+#VOID\r
+#EfiInvd (\r
+# VOID\r
+#)\r
+ASM_PFX(EfiInvd):\r
+    invd\r
+    ret\r
+#EfiInvd ENDP\r
+\r
+#VOID\r
+#EfiCpuid (IN UINT32 RegisterInEax,\r
+#          OUT EFI_CPUID_REGISTER *Reg OPTIONAL)\r
+ASM_PFX(EfiCpuid):\r
+    pushl %ebp\r
+    movl %esp, %ebp\r
+    pushl %ebx\r
+    pushl %esi\r
+    pushl %edi\r
+    pushal\r
+\r
+    movl   8(%ebp), %eax           #RegisterInEax\r
+    cpuid\r
+    cmpl   $0, 0xC(%ebp)           # Reg\r
+    je     L1\r
+    movl        0xC(%ebp), %edi         # Reg\r
+\r
+    movl        %eax, (%edi)        # Reg->RegEax\r
+    movl        %ebx, 4(%edi)         # Reg->RegEbx\r
+    movl        %ecx, 8(%edi)         # Reg->RegEcx\r
+    movl        %edx, 0xC(%edi)         # Reg->RegEdx\r
+\r
+L1:\r
+    popal\r
+    popl        %edi\r
+    popl        %esi\r
+    popl        %ebx\r
+    popl        %ebp\r
+\r
+    ret\r
+#EfiCpuid ENDP\r
+\r
+\r
+#UINT64\r
+#EfiReadMsr (\r
+#  IN UINT32 Index\r
+#  );\r
+ASM_PFX(EfiReadMsr):\r
+    movl   4(%esp), %ecx           # Index\r
+    rdmsr\r
+    ret\r
+#EfiReadMsr ENDP\r
+\r
+#VOID\r
+#EfiWriteMsr (\r
+#  IN   UINT32  Index,\r
+#  IN   UINT64  Value\r
+#  );\r
+ASM_PFX(EfiWriteMsr):\r
+    movl   4(%esp), %ecx         # Index\r
+    movl   8(%esp), %eax         # DWORD PTR Value[0]\r
+    movl   0xC(%esp), %edx         # DWORD PTR Value[4]\r
+    wrmsr\r
+    ret\r
+#EfiWriteMsr ENDP\r
+\r
+#UINT64\r
+#EfiReadTsc (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiReadTsc):\r
+    rdtsc\r
+    ret\r
+#EfiReadTsc ENDP\r
+\r
+#VOID\r
+#EfiDisableCache (\r
+#  VOID\r
+#)\r
+ASM_PFX(EfiDisableCache):\r
+    movl  %cr0, %eax\r
+    bswapl %eax\r
+    andb  $0x60, %al\r
+    cmpb  $0x60, %al\r
+    je    L2\r
+    movl  %cr0, %eax\r
+    orl   $0x60000000, %eax\r
+    movl  %eax, %cr0\r
+    wbinvd\r
+L2:\r
+    ret\r
+#EfiDisableCache ENDP\r
+\r
+#VOID\r
+#EfiEnableCache (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiEnableCache):\r
+    wbinvd\r
+    movl  %cr0, %eax\r
+    andl  $0x9fffffff, %eax\r
+    movl  %eax, %cr0\r
+    ret\r
+#EfiEnableCache ENDP\r
+\r
+#UINT32\r
+#EfiGetEflags (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiGetEflags):\r
+    pushfl\r
+    popl %eax\r
+    ret\r
+#EfiGetEflags ENDP\r
+\r
+#VOID\r
+#EfiDisableInterrupts (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiDisableInterrupts):\r
+    cli\r
+    ret\r
+#EfiDisableInterrupts ENDP\r
+\r
+#VOID\r
+#EfiEnableInterrupts (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiEnableInterrupts):\r
+    sti\r
+    ret\r
+#EfiEnableInterrupts ENDP\r
+\r
+#VOID\r
+#EfiCpuidExt (\r
+#  IN   UINT32              RegisterInEax,\r
+#  IN   UINT32              CacheLevel,\r
+#  OUT  EFI_CPUID_REGISTER  *Regs\r
+#  )\r
+ASM_PFX(EfiCpuidExt):\r
+    push   %ebx\r
+    push   %edi\r
+    push   %esi\r
+    pushal\r
+\r
+    movl   0x30(%esp), %eax           # RegisterInEax\r
+    movl   0x34(%esp), %ecx           # CacheLevel\r
+    cpuid\r
+    movl   0x38(%esp), %edi           # DWORD PTR Regs\r
+\r
+    movl   %eax, (%edi)                 # Reg->RegEax\r
+    movl   %ebx, 4(%edi)                # Reg->RegEbx\r
+    movl   %ecx, 8(%edi)                # Reg->RegEcx\r
+    movl   %edx, 0xC(%edi)              # Reg->RegEdx\r
+\r
+    popal\r
+    pop    %esi\r
+    pop    %edi\r
+    pop    %ebx\r
+    ret\r
+#EfiCpuidExt ENDP\r
+\r
+\r
+\r