+++ /dev/null
-/** @file\r
- I2C PEI Lib Instance.\r
-\r
- Copyright (c) 1999- 2015, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#ifndef I2C_PEI_REGS_H\r
-#define I2C_PEI_REGS_H\r
-\r
-#include "PiPei.h"\r
-\r
-#define R_PCH_LPC_PMC_BASE 0x44\r
-#define B_PCH_LPC_PMC_BASE_BAR 0xFFFFFE00\r
-#define R_PCH_PMC_FUNC_DIS 0x34 // Function Disable Register\r
-#define PCIEX_BASE_ADDRESS 0xE0000000\r
-#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC7 BIT7 // LPSS SPI Disable\r
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC6 BIT6 // LPSS HSUART #2 Disable\r
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC5 BIT5 // LPSS HSUART #1 Disable\r
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC4 BIT4 // LPSS I2S Disable\r
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC3 BIT3 // LPSS PCM Disable\r
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC2 BIT2 // LPSS I2C #2 Disable\r
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC1 BIT1 // LPSS I2C #1 Disable\r
-#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC0 BIT0 // LPSS DMA Disable\r
-\r
-\r
-#define DEFAULT_PCI_BUS_NUMBER_PCH 0\r
-\r
-#define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command\r
-#define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA\r
-#define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA\r
-#define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List\r
-#define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status\r
-#define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable\r
-#define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable\r
-#define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable\r
-#define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable\r
-\r
-#define R_PCH_LPSS_I2C_BAR 0x10 // BAR\r
-#define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address\r
-#define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1\r
-#define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address\r
-#define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space\r
-\r
-#define NUM_RETRIES 0xFFFF\r
-\r
-//\r
-// LPIO I2C Module Memory Space Registers\r
-//\r
-#define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset\r
-#define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r
-#define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset\r
-\r
-#define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters\r
-\r
-#define bit(a) 1 << (a)\r
-\r
-//\r
-// MMIO Register Definitions\r
-//\r
-\r
-#define I2C0_REG_SPACE_ADDR_BASE 0xFF138000 //01K\r
-\r
-#define R_IC_CON ( 0x00) // I2C Control\r
-#define B_IC_RESTART_EN BIT5\r
-#define B_IC_SLAVE_DISABLE BIT6\r
-#define V_SPEED_STANDARD 0x02\r
-#define V_SPEED_FAST 0x04\r
-#define V_SPEED_HIGH 0x06\r
-#define B_MASTER_MODE BIT0\r
-\r
-#define R_IC_TAR ( 0x04) // I2C Target Address\r
-#define IC_TAR_10BITADDR_MASTER BIT12\r
-\r
-#define R_IC_SAR ( 0x08) // I2C Slave Address\r
-#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address\r
-#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command\r
-\r
-#define B_READ_CMD BIT8 // 1 = read, 0 = write\r
-#define B_CMD_STOP BIT9 // 1 = STOP\r
-#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN\r
-\r
-#define V_WRITE_CMD_MASK ( 0xFF)\r
-\r
-#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count\r
-#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count\r
-#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count\r
-#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count\r
-#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count\r
-#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count\r
-#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status\r
-#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask\r
-#define I2C_INTR_GEN_CALL BIT11 // General call received\r
-#define I2C_INTR_START_DET BIT10\r
-#define I2C_INTR_STOP_DET BIT9\r
-#define I2C_INTR_ACTIVITY BIT8\r
-#define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r
-#define I2C_INTR_TX_EMPTY BIT4\r
-#define I2C_INTR_TX_OVER BIT3\r
-#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r
-#define I2C_INTR_RX_OVER BIT1\r
-#define I2C_INTR_RX_UNDER BIT0\r
-#define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status\r
-#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold\r
-#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold\r
-#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts\r
-#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt\r
-#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt\r
-#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt\r
-#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt\r
-#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt\r
-#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt\r
-#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt\r
-#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt\r
-#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt\r
-#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt\r
-#define R_IC_ENABLE ( 0x6C) // I2C Enable\r
-#define R_IC_STATUS ( 0x70) // I2C Status\r
-\r
-#define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits\r
-\r
-#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.\r
-#define STAT_RFF BIT4 // RX FIFO is completely full\r
-#define STAT_RFNE BIT3 // RX FIFO is not empty\r
-#define STAT_TFE BIT2 // TX FIFO is completely empty\r
-#define STAT_TFNF BIT1 // TX FIFO is not full\r
-\r
-#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register\r
-#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register\r
-#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register\r
-#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register\r
-#define R_IC_DMA_CR ( 0x88) // DMA Control Register\r
-#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level\r
-#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level\r
-#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register\r
-#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register\r
-#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register\r
-#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register\r
-#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID\r
-#define R_IC_COMP_TYPE ( 0xFC) // Component Type\r
-\r
-#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD\r
-#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4\r
-#define I2C_FS_SCL_HCNT_VALUE_100M 0x54\r
-#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a\r
-#define I2C_HS_SCL_HCNT_VALUE_100M 0x7\r
-#define I2C_HS_SCL_LCNT_VALUE_100M 0xE\r
-\r
-//\r
-// FIFO write workaround value.\r
-//\r
-#define FIFO_WRITE_DELAY 2\r
-#define IC_TAR_10BITADDR_MASTER BIT12\r
-#define FIFO_SIZE 32\r
-#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status\r
-#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask\r
-#define I2C_INTR_GEN_CALL BIT11 // General call received\r
-#define I2C_INTR_START_DET BIT10\r
-#define I2C_INTR_STOP_DET BIT9\r
-#define I2C_INTR_ACTIVITY BIT8\r
-#define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r
-#define I2C_INTR_TX_EMPTY BIT4\r
-#define I2C_INTR_TX_OVER BIT3\r
-#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r
-#define I2C_INTR_RX_OVER BIT1\r
-#define I2C_INTR_RX_UNDER BIT0\r
-\r
-/**\r
- Programe all I2C controllers on LPSS. \r
- \r
- I2C0 is function 1 of LPSS. I2C1 is function 2 of LPSS, etc..\r
-\r
- @param VOID\r
-\r
- @return EFI_SUCCESS\r
-**/\r
-EFI_STATUS\r
-ProgramPciLpssI2C (\r
- VOID\r
- );\r
-\r
-/**\r
- Reads a Byte from I2C Device.\r
- \r
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r
- @param SlaveAddress Device Address from which the byte value has to be read\r
- @param Offset Offset from which the data has to be read\r
- @param *Byte Address to which the value read has to be stored\r
- @param Start Whether a RESTART is issued before the byte is sent or received\r
- @param End Whether STOP is generated after a data byte is sent or received \r
- \r
- @return EFI_SUCCESS If the byte value has been successfully read\r
- @return EFI_DEVICE_ERROR Operation Failed, Device Error\r
-**/\r
-EFI_STATUS\r
-ByteReadI2CBasic(\r
- IN UINT8 I2cControllerIndex,\r
- IN UINT8 SlaveAddress,\r
- IN UINTN ReadBytes,\r
- OUT UINT8 *ReadBuffer,\r
- IN UINT8 Start,\r
- IN UINT8 End\r
- );\r
-\r
-/**\r
- Writes a Byte to I2C Device.\r
- \r
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r
- @param SlaveAddress Device Address from which the byte value has to be written\r
- @param Offset Offset from which the data has to be read\r
- @param *Byte Address to which the value written is stored\r
- @param Start Whether a RESTART is issued before the byte is sent or received\r
- @param End Whether STOP is generated after a data byte is sent or received \r
- \r
- @return EFI_SUCCESS IF the byte value has been successfully written\r
- @return EFI_DEVICE_ERROR Operation Failed, Device Error\r
-**/\r
-EFI_STATUS\r
-ByteWriteI2CBasic(\r
- IN UINT8 I2cControllerIndex,\r
- IN UINT8 SlaveAddress,\r
- IN UINTN WriteBytes,\r
- IN UINT8 *WriteBuffer,\r
- IN UINT8 Start,\r
- IN UINT8 End\r
- );\r
-\r
-/**\r
- Reads a Byte from I2C Device.\r
- \r
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r
- @param SlaveAddress Device Address from which the byte value has to be read\r
- @param Offset Offset from which the data has to be read\r
- @param ReadBytes Number of bytes to be read\r
- @param *ReadBuffer Address to which the value read has to be stored\r
- \r
- @return EFI_SUCCESS IF the byte value has been successfully read\r
- @return EFI_DEVICE_ERROR Operation Failed, Device Error\r
-**/\r
-EFI_STATUS\r
-ByteReadI2C(\r
- IN UINT8 I2cControllerIndex,\r
- IN UINT8 SlaveAddress,\r
- IN UINT8 Offset,\r
- IN UINTN ReadBytes,\r
- OUT UINT8 *ReadBuffer\r
- );\r
-\r
-/**\r
- Writes a Byte to I2C Device.\r
- \r
- @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r
- @param SlaveAddress Device Address from which the byte value has to be written\r
- @param Offset Offset from which the data has to be written\r
- @param WriteBytes Number of bytes to be written\r
- @param *Byte Address to which the value written is stored\r
- \r
- @return EFI_SUCCESS IF the byte value has been successfully read\r
- @return EFI_DEVICE_ERROR Operation Failed, Device Error\r
-**/\r
-EFI_STATUS\r
-ByteWriteI2C(\r
- IN UINT8 I2cControllerIndex,\r
- IN UINT8 SlaveAddress,\r
- IN UINT8 Offset,\r
- IN UINTN WriteBytes,\r
- IN UINT8 *WriteBuffer\r
- );\r
-\r
-#endif\r
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