+++ /dev/null
-/**@file\r
- Clock generator setting for multiplatform.\r
-\r
- This file includes package header files, library classes.\r
-\r
- Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
- \r\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- \r\r
-**/\r
-\r
-#ifndef _BOARD_CLK_GEN_H_\r
-#define _BOARD_CLK_GEN_H_\r
-\r
-#include <PiPei.h>\r
-#include <Library/HobLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/SmbusLib.h>\r
-#include <Ppi/Smbus.h>\r
-#include <IndustryStandard/SmBus.h>\r
-#include <Guid/PlatformInfo.h>\r
-\r
-\r
-#define CLOCK_GENERATOR_ADDRESS 0xd2\r
-\r
-#define CLOCK_GENERATOR_SEETINGS_TABLET {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}\r
-#define CLOCK_GENERATOR_SETTINGS_MOBILE {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}\r
-#define CLOCK_GENERATOR_SETTINGS_DESKTOP {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}\r
-\r
-typedef enum {\r
- ClockGeneratorCk410,\r
- ClockGeneratorCk505,\r
- ClockGeneratorMax\r
-} CLOCK_GENERATOR_TYPE;\r
-\r
-typedef struct {\r
- CLOCK_GENERATOR_TYPE ClockType;\r
- UINT8 ClockId;\r
- UINT8 SpreadSpectrumByteOffset;\r
- UINT8 SpreadSpectrumBitOffset;\r
-} CLOCK_GENERATOR_DETAILS;\r
-\r
-#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20\r
-\r
-//\r
-// CK410 Definitions\r
-//\r
-#define CK410_GENERATOR_ID 0x65\r
-#define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE 1\r
-#define CK410_GENERATOR_SPREAD_SPECTRUM_BIT BIT0\r
-#define CK410_GENERATOR_CLOCK_FREERUN_BYTE 4\r
-#define CK410_GENERATOR_CLOCK_FREERUN_BIT (BIT0 | BIT1 | BIT2)\r
-\r
-//\r
-// CK505 Definitions\r
-//\r
-#define VF_CK505_GENERATOR_ID 0x5\r
-#define CK505_GENERATOR_ID 0x5 // Confirmed readout is 5\r
-#define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE 4\r
-#define CK505_GENERATOR_SPREAD_SPECTRUM_BIT (BIT0 | BIT1)\r
-#define CK505_GENERATOR_PERCENT_SPREAD_BYTE 1\r
-#define CK505_GENERATOR_PERCENT_MASK ~(0xE)\r
-#define CK505_GENERATOR_PERCENT_250_VALUE 0xC\r
-#define CK505_GENERATOR_PERCENT_050_VALUE 0x4\r
-#define CK505_GENERATOR_PERCENT_000_VALUE 0x2\r
-\r
-//\r
-// IDT Definitions\r
-//\r
-#define IDT_GENERATOR_ID_REVA 0x1 //IDT Rev A\r
-#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BYTE 0\r
-#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BIT BIT0\r
-#define IDTRevA_GENERATOR_PERCENT_SPREAD_BYTE 5\r
-#define IDTRevA_GENERATOR_PERCENT_250_VALUE 0xF\r
-#define IDTRevA_GENERATOR_PERCENT_050_VALUE 0x3\r
-#define IDTRevA_GENERATOR_PERCENT_000_VALUE 0xE\r
-#define IDTRevA_GENERATOR_PERCENT_MASK ~(0xF)\r
-\r
-#define IDT_GENERATOR_ID_REVB 0x11 //IDT RevB\r
-#define IDT_GENERATOR_ID_REVD 0x21 //IDT RevD\r
-\r
-//\r
-// CLOCK CONTROLLER\r
-// SmBus address to read DIMM SPD\r
-//\r
-#define SMBUS_BASE_ADDRESS 0xEFA0\r
-#define SMBUS_BUS_DEV_FUNC 0x1F0300\r
-#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 4\r
-#define SMBUS_ADDR_CH_A_1 0xA0\r
-#define SMBUS_ADDR_CH_A_2 0xA2\r
-#define SMBUS_ADDR_CH_B_1 0xA4\r
-#define SMBUS_ADDR_CH_B_2 0xA6\r
-\r
-//\r
-// Bits for FWH_DEC_EN1\97Firmware Hub Decode Enable Register (LPC I/F\97D31:F0)\r
-//\r
-#define B_ICH_LPC_FWH_BIOS_DEC_F0 0x4000\r
-#define B_ICH_LPC_FWH_BIOS_DEC_E0 0x1000\r
-#define B_ICH_LPC_FWH_BIOS_DEC_E8 0x2000\r
-#define B_ICH_LPC_FWH_BIOS_LEG_F 0x0080\r
-#define B_ICH_LPC_FWH_BIOS_LEG_E 0x0040\r
-\r
-\r
-//\r
-// An arbitrary maximum length for clock generator buffers\r
-//\r
-#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20\r
-\r
-//\r
-// SmBus Bus Device Function and Register Definitions\r
-//\r
-#define SMBUS_BUS_NUM 0\r
-#define SMBUS_DEV_NUM 31\r
-#define SMBUS_FUNC_NUM 3\r
-#define SMBUS_BUS_DEV_FUNC_NUM \\r
- SB_PCI_CFG_ADDRESS(SMBUS_BUS_NUM, SMBUS_DEV_NUM, SMBUS_FUNC_NUM, 0)\r
-\r
-//\r
-//ICH7: SMBus I/O Space Equates;\r
-//\r
-#define BIT_SLAVE_ADDR BIT00\r
-#define BIT_COMMAND BIT01\r
-#define BIT_DATA BIT02\r
-#define BIT_COUNT BIT03\r
-#define BIT_WORD BIT04\r
-#define BIT_CONTROL BIT05\r
-#define BIT_PEC BIT06\r
-#define BIT_READ BIT07\r
-#define SMBUS_IO_READ_BIT BIT00\r
-\r
-\r
-#define SMB_CMD_QUICK 0x00\r
-#define SMB_CMD_BYTE 0x04\r
-#define SMB_CMD_BYTE_DATA 0x08\r
-#define SMB_CMD_WORD_DATA 0x0C\r
-#define SMB_CMD_PROCESS_CALL 0x10\r
-#define SMB_CMD_BLOCK 0x14\r
-#define SMB_CMD_I2C_READ 0x18\r
-#define SMB_CMD_RESERVED 0x1c\r
-\r
-#define HST_STS_BYTE_DONE 0x80\r
-#define SMB_HST_STS 0x000\r
-#define SMB_HST_CNT 0x002\r
-#define SMB_HST_CMD 0x003\r
-#define SMB_HST_ADD 0x004\r
-#define SMB_HST_DAT_0 0x005\r
-#define SMB_HST_DAT_1 0x006\r
-#define SMB_HST_BLK_DAT 0x007\r
-#define SMB_PEC 0x008\r
-#define SMB_RCV_SLVA 0x009\r
-#define SMB_SLV_DAT 0x00A\r
-#define SMB_AUX_STS 0x00C\r
-#define SMB_AUX_CTL 0x00D\r
-#define SMB_SMLINK_PIN_CTL 0x00E\r
-#define SMB_SMBUS_PIN_CTL 0x00F\r
-#define SMB_SLV_STS 0x010\r
-#define SMB_SLV_CMD 0x011\r
-#define SMB_NTFY_DADDR 0x014\r
-#define SMB_NTFY_DLOW 0x016\r
-#define SMB_NTFY_DHIGH 0x017\r
-\r
-//\r
-// PCI Register Definitions - use SmbusPolicyPpi->PciAddress + offset listed below\r
-//\r
-#define R_COMMAND 0x04 // PCI Command Register, 16bit\r
-#define B_IOSE 0x01 // RW\r
-#define R_BASE_ADDRESS 0x20 // PCI BAR for SMBus I/O\r
-#define B_BASE_ADDRESS 0xFFE0 // RW\r
-#define R_HOST_CONFIGURATION 0x40 // SMBus Host Configuration Register\r
-#define B_HST_EN 0x01 // RW\r
-#define B_SMB_SMI_EN 0x02 // RW\r
-#define B_I2C_EN 0x04 // RW\r
-//\r
-// I/O Register Definitions - use SmbusPolicyPpi->BaseAddress + offset listed below\r
-//\r
-#define HOST_STATUS_REGISTER 0x00 // Host Status Register R/W\r
-#define HST_STS_HOST_BUSY 0x01 // RO\r
-#define HST_STS_INTR 0x02 // R/WC\r
-#define HST_STS_DEV_ERR 0x04 // R/WC\r
-#define HST_STS_BUS_ERR 0x08 // R/WC\r
-#define HST_STS_FAILED 0x10 // R/WC\r
-#define SMBUS_B_SMBALERT_STS 0x20 // R/WC\r
-#define HST_STS_INUSE 0x40 // R/WC\r
-#define SMBUS_B_BYTE_DONE_STS 0x80 // R/WC\r
-#define SMBUS_B_HSTS_ALL 0xFF // R/WC\r
-#define HOST_CONTROL_REGISTER 0x02 // Host Control Register R/W\r
-#define HST_CNT_INTREN 0x01 // RW\r
-#define HST_CNT_KILL 0x02 // RW\r
-#define SMBUS_B_SMB_CMD 0x1C // RW\r
-#define SMBUS_V_SMB_CMD_QUICK 0x00\r
-#define SMBUS_V_SMB_CMD_BYTE 0x04\r
-#define SMBUS_V_SMB_CMD_BYTE_DATA 0x08\r
-#define SMBUS_V_SMB_CMD_WORD_DATA 0x0C\r
-#define SMBUS_V_SMB_CMD_PROCESS_CALL 0x10\r
-#define SMBUS_V_SMB_CMD_BLOCK 0x14\r
-#define SMBUS_V_SMB_CMD_IIC_READ 0x18\r
-#define SMBUS_B_LAST_BYTE 0x20 // WO\r
-#define HST_CNT_START 0x40 // WO\r
-#define HST_CNT_PEC_EN 0x80 // RW\r
-#define HOST_COMMAND_REGISTER 0x03 // Host Command Register R/W\r
-#define XMIT_SLAVE_ADDRESS_REGISTER 0x04 // Transmit Slave Address Register R/W\r
-#define SMBUS_B_RW_SEL 0x01 // RW\r
-#define SMBUS_B_ADDRESS 0xFE // RW\r
-#define HOST_DATA_0_REGISTER 0x05 // Data 0 Register R/W\r
-#define HOST_DATA_1_REGISTER 0x06 // Data 1 Register R/W\r
-#define HOST_BLOCK_DATA_BYTE_REGISTER 0x07 // Host Block Data Register R/W\r
-#define SMBUS_R_PEC 0x08 // Packet Error Check Data Register R/W\r
-#define SMBUS_R_RSA 0x09 // Receive Slave Address Register R/W\r
-#define SMBUS_B_SLAVE_ADDR 0x7F // RW\r
-#define SMBUS_R_SD 0x0A // Receive Slave Data Register R/W\r
-#define SMBUS_R_AUXS 0x0C // Auxiliary Status Register R/WC\r
-#define SMBUS_B_CRCE 0x01 //R/WC\r
-#define AUXILIARY_CONTROL_REGISTER 0x0D // Auxiliary Control Register R/W\r
-#define SMBUS_B_AAC 0x01 //R/W\r
-#define SMBUS_B_E32B 0x02 //R/W\r
-#define SMBUS_R_SMLC 0x0E // SMLINK Pin Control Register R/W\r
-#define SMBUS_B_SMLINK0_CUR_STS 0x01 // RO\r
-#define SMBUS_B_SMLINK1_CUR_STS 0x02 // RO\r
-#define SMBUS_B_SMLINK_CLK_CTL 0x04 // RW\r
-#define SMBUS_R_SMBC 0x0F // SMBus Pin Control Register R/W\r
-#define SMBUS_B_SMBCLK_CUR_STS 0x01 // RO\r
-#define SMBUS_B_SMBDATA_CUR_STS 0x02 // RO\r
-#define SMBUS_B_SMBCLK_CTL 0x04 // RW\r
-#define SMBUS_R_SSTS 0x10 // Slave Status Register R/WC\r
-#define SMBUS_B_HOST_NOTIFY_STS 0x01 // R/WC\r
-#define SMBUS_R_SCMD 0x11 // Slave Command Register R/W\r
-#define SMBUS_B_HOST_NOTIFY_INTREN 0x01 // R/W\r
-#define SMBUS_B_HOST_NOTIFY_WKEN 0x02 // R/W\r
-#define SMBUS_B_SMBALERT_DIS 0x04 // R/W\r
-#define SMBUS_R_NDA 0x14 // Notify Device Address Register RO\r
-#define SMBUS_B_DEVICE_ADDRESS 0xFE // RO\r
-#define SMBUS_R_NDLB 0x16 // Notify Data Low Byte Register RO\r
-#define SMBUS_R_NDHB 0x17 // Notify Data High Byte Register RO\r
-#define BUS_TRIES 3 // How many times to retry on Bus Errors\r
-#define SMBUS_NUM_RESERVED 21 // Number of device addresses that are\r
- // reserved by the SMBus spec.\r
-#define SMBUS_ADDRESS_ARP 0xC2 >> 1\r
-#define SMBUS_DATA_PREPARE_TO_ARP 0x01\r
-#define SMBUS_DATA_RESET_DEVICE 0x02\r
-#define SMBUS_DATA_GET_UDID_GENERAL 0x03\r
-#define SMBUS_DATA_ASSIGN_ADDRESS 0x04\r
-#define SMBUS_GET_UDID_LENGTH 17 // 16 byte UDID + 1 byte address\r
-\r
-\r
-EFI_STATUS\r
-ConfigurePlatformClocks (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
- IN VOID *SmbusPpi\r
- );\r
-\r
-\r
-#endif\r
projects / mirror_edk2.git / blobdiff