+++ /dev/null
-/*++\r
-\r
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
- \r\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- \r\r
-\r
-Module Name:\r
-\r
- SlotConfig.c\r
-\r
-Abstract:\r
-\r
- Sets platform/SKU specific expansion slot information.\r
-\r
-\r
-\r
-\r
---*/\r
-\r
-#include "PlatformDxe.h"\r
-#include <Protocol/SmbiosSlotPopulation.h>\r
-#include <IndustryStandard/Pci22.h>\r
-\r
-\r
-//\r
-// Default bus number for the bridge\r
-//\r
-#define DEF_BUS_CONFIG 0x0101\r
-#define DEF_BUS 0x01\r
-\r
-//\r
-// Data structures for slot information\r
-//\r
-typedef struct {\r
- UINT16 SmbiosSlotId;\r
- UINT8 Bus;\r
- UINT8 Dev;\r
- UINT8 Function;\r
- UINT8 TargetDevice;\r
-} EFI_PCI_SLOT_BRIDGE_INFO;\r
-\r
-//\r
-// Product specific bridge to slot routing information\r
-//\r
-EFI_PCI_SLOT_BRIDGE_INFO mSlotBridgeTable[] = {\r
- {\r
- 0x01, //PCIe x1 ICH (Bridge B0:D28:F1)\r
- DEFAULT_PCI_BUS_NUMBER_PCH,\r
- PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,\r
- PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2,\r
- 0\r
- }\r
-};\r
-\r
-UINTN mSlotBridgeTableSize =\r
- sizeof(mSlotBridgeTable) / sizeof(EFI_PCI_SLOT_BRIDGE_INFO);\r
-\r
-//\r
-// Slot entry table for IBX RVP\r
-//\r
-EFI_SMBIOS_SLOT_ENTRY mSlotEntries[] = {\r
- {0x06, FALSE, TRUE}, // PCIe x16 Slot 1 (NOT USED)\r
- {0x04, FALSE, TRUE}, // PCIe x16 Slot 2 (NOT USED)\r
- {0x03, FALSE, TRUE}, // PCIe x4 Slot (NOT USED)\r
- {0x02, FALSE, FALSE}, // Mini PCIe x1 Slot\r
- {0x15, FALSE, TRUE}, // PCIe x1 Slot 2 (NOT USED)\r
- {0x16, FALSE, TRUE}, // PCIe x1 Slot 3 (NOT USED)\r
- {0x07, FALSE, FALSE}, // PCI Slot 1\r
- {0x18, FALSE, TRUE}, // PCI Slot 2 (NOT USED)\r
- {0x17, FALSE, TRUE}, // PCI Slot 3 (NOT USED)\r
-};\r
-\r
-EFI_SMBIOS_SLOT_POPULATION_INFO mSlotInformation = {\r
- sizeof(mSlotEntries) / sizeof(EFI_SMBIOS_SLOT_ENTRY),\r
- mSlotEntries\r
-};\r
-\r
-\r