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MdePkg/BaseLib: BaseLib for RISCV64 architecture
authorAbner Chang <abner.chang@hpe.com>
Tue, 7 Apr 2020 07:53:22 +0000 (15:53 +0800)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Thu, 7 May 2020 03:17:15 +0000 (03:17 +0000)
commit7601b251fd5cfd6cd70d40bc9c88b3b371143654
treef791c1686f91686e03b94b58bc36b99a3d0775a9tree
parentd3abb40d77e770e07708a31e757d8f11e513293ccommit | diff
MdePkg/BaseLib: BaseLib for RISCV64 architecture

Add RISC-V RV64 BaseLib functions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
13 files changed:
MdePkg/Include/Library/BaseLib.h diff | blob | blame | history
MdePkg/Library/BaseLib/BaseLib.inf diff | blob | blame | history
MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/CpuPause.c [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/FlushCache.S [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S [new file with mode: 0644] blob
MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S [new file with mode: 0644] blob
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