]> git.proxmox.com Git - mirror_edk2.git/commitdiff
ArmPkg/IndustryStandard: 32b/64b agnostic FF-A, Mm SVC and Std SMC IDs
authorEtienne Carriere <etienne.carriere@linaro.org>
Mon, 9 Aug 2021 15:19:42 +0000 (17:19 +0200)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Wed, 11 Aug 2021 11:32:32 +0000 (11:32 +0000)
Defines ARM_SVC_ID_FFA_* and ARM_SVC_ID_SP_* identifiers for 32bit
function IDs as per SMCCC specification. Defines also generic ARM
SVC identifier macros to wrap 32bit or 64bit identifiers upon target
built architecture.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
ArmPkg/Include/IndustryStandard/ArmMmSvc.h
ArmPkg/Include/IndustryStandard/ArmStdSmc.h

index 65b8343ade61acfdc196e2e6ee09f98e2edccd0d..ebcb54b28b168d6243baccd46e2049ae57e1125a 100644 (file)
 #define ARM_FFA_SVC_H_\r
 \r
 #define ARM_SVC_ID_FFA_VERSION_AARCH32                  0x84000063\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32      0x8400006F\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32     0x84000070\r
 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64      0xC400006F\r
 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64     0xC4000070\r
 \r
+/* Generic IDs when using AArch32 or AArch64 execution state */\r
+#ifdef MDE_CPU_AARCH64\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ     ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP    ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64\r
+#endif\r
+#ifdef MDE_CPU_ARM\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ     ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32\r
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP    ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32\r
+#endif\r
+\r
 #define SPM_MAJOR_VERSION_FFA                           1\r
 #define SPM_MINOR_VERSION_FFA                           0\r
 \r
index 33d60ccf17bcea0897a0d186ec308a129a36cd78..deb3bc99d2ad5669e7870c638cba9a018331244d 100644 (file)
  * privileged operations on its behalf.\r
  */\r
 #define ARM_SVC_ID_SPM_VERSION_AARCH32             0x84000060\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32       0x84000061\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32   0x84000064\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32   0x84000065\r
 #define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64       0xC4000061\r
 #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64   0xC4000064\r
 #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64   0xC4000065\r
 \r
+/* Generic IDs when using AArch32 or AArch64 execution state */\r
+#ifdef MDE_CPU_AARCH64\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE               ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES       ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES       ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64\r
+#endif\r
+#ifdef MDE_CPU_ARM\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE               ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES       ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES       ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32\r
+#endif\r
+\r
 #define SET_MEM_ATTR_DATA_PERM_MASK       0x3\r
 #define SET_MEM_ATTR_DATA_PERM_SHIFT        0\r
 #define SET_MEM_ATTR_DATA_PERM_NO_ACCESS    0\r
index 67afb0ea2d3da9f4d1f73903de5d48bb766589bd..9116a291dadddee7f6ca5328df09b7b705f936db 100644 (file)
 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH32          0x84000041\r
 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH64          0xC4000041\r
 \r
+/* Generic ID when using AArch32 or AArch64 execution state */\r
+#ifdef MDE_CPU_AARCH64\r
+#define ARM_SMC_ID_MM_COMMUNICATE   ARM_SMC_ID_MM_COMMUNICATE_AARCH64\r
+#endif\r
+#ifdef MDE_CPU_ARM\r
+#define ARM_SMC_ID_MM_COMMUNICATE   ARM_SMC_ID_MM_COMMUNICATE_AARCH32\r
+#endif\r
+\r
 /* MM return error codes */\r
 #define ARM_SMC_MM_RET_SUCCESS              0\r
 #define ARM_SMC_MM_RET_NOT_SUPPORTED       -1\r