\r
#include <ArmPlatform.h>\r
\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
-\r
-ASM_PFX(ArmPlatformPeiBootAction):\r
+ASM_FUNC(ArmPlatformPeiBootAction)\r
bx lr\r
\r
//UINTN\r
//ArmPlatformGetCorePosition (\r
// IN UINTN MpId\r
// );\r
-ASM_PFX(ArmPlatformGetCorePosition):\r
+ASM_FUNC(ArmPlatformGetCorePosition)\r
and r1, r0, #ARM_CORE_MASK\r
and r0, r0, #ARM_CLUSTER_MASK\r
add r0, r1, r0, LSR #7\r
//ArmPlatformIsPrimaryCore (\r
// IN UINTN MpId\r
// );\r
-ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ASM_FUNC(ArmPlatformIsPrimaryCore)\r
// Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
// with cpu_id[0:3] and cluster_id[4:7]\r
- LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r1)\r
+ MOV32 (r1, ARM_CTA15A7_SCC_CFGREG48)\r
ldr r1, [r1]\r
lsr r1, #24\r
\r
orr r1, r1, r2\r
\r
// Keep the Cluster ID and Core ID from the MPID\r
- LoadConstantToReg (ARM_CLUSTER_MASK | ARM_CORE_MASK, r2)\r
+ MOV32 (r2, ARM_CLUSTER_MASK | ARM_CORE_MASK)\r
and r0, r0, r2\r
\r
// Compare mpid and boot cpu from ARM_SCC_CFGREG48\r
//ArmPlatformGetPrimaryCoreMpId (\r
// VOID\r
// );\r
-ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
// Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
// with cpu_id[0:3] and cluster_id[4:7]\r
- LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r0)\r
+ MOV32 (r0, ARM_CTA15A7_SCC_CFGREG48)\r
ldr r0, [r0]\r
lsr r0, #24\r
\r
#include <AsmMacroIoLib.h>\r
#include <Library/ArmLib.h>\r
\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
-GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
-\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
-\r
//UINTN\r
//ArmPlatformGetPrimaryCoreMpId (\r
// VOID\r
// );\r
-ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
- ldr r0, [r0]\r
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
+ MOV32 (r0, FixedPcdGet32 (PcdArmPrimaryCore))\r
bx lr\r
\r
//UINTN\r
//ArmPlatformIsPrimaryCore (\r
// IN UINTN MpId\r
// );\r
-ASM_PFX(ArmPlatformIsPrimaryCore):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
- ldr r1, [r1]\r
+ASM_FUNC(ArmPlatformIsPrimaryCore)\r
+ MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))\r
and r0, r0, r1\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
- ldr r1, [r1]\r
+ MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCore))\r
cmp r0, r1\r
moveq r0, #1\r
movne r0, #0\r
//ArmPlatformGetCorePosition (\r
// IN UINTN MpId\r
// );\r
-ASM_PFX(ArmPlatformGetCorePosition):\r
+ASM_FUNC(ArmPlatformGetCorePosition)\r
and r0, r0, #ARM_CORE_MASK\r
bx lr\r
\r
-ASM_PFX(ArmPlatformPeiBootAction):\r
+ASM_FUNC(ArmPlatformPeiBootAction)\r
bx lr\r
\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
#\r
\r
#include <AsmMacroIoLibV8.h>\r
-#include <Base.h>\r
#include <Library/ArmLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
-GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
-\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r
-\r
-ASM_PFX(ArmPlatformPeiBootAction):\r
+ASM_FUNC(ArmPlatformPeiBootAction)\r
ret\r
\r
//UINTN\r
//ArmPlatformGetPrimaryCoreMpId (\r
// VOID\r
// );\r
-ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r
- ldrh w0, [x0]\r
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))\r
ret\r
\r
# IN None\r
# OUT x0 = number of cores present in the system\r
-ASM_PFX(ArmGetCpuCountPerCluster):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, x0)\r
- ldrh w0, [x0]\r
+ASM_FUNC(ArmGetCpuCountPerCluster)\r
+ MOV32 (w0, FixedPcdGet32 (PcdCoreCount))\r
ret\r
\r
//UINTN\r
//ArmPlatformIsPrimaryCore (\r
// IN UINTN MpId\r
// );\r
-ASM_PFX(ArmPlatformIsPrimaryCore):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1)\r
- ldrh w1, [x1]\r
+ASM_FUNC(ArmPlatformIsPrimaryCore)\r
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))\r
and x0, x0, x1\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x1)\r
- ldrh w1, [x1]\r
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))\r
cmp w0, w1\r
b.ne 1f\r
mov x0, #1\r
// IN UINTN MpId\r
// );\r
// With this function: CorePos = (ClusterId * 4) + CoreId\r
-ASM_PFX(ArmPlatformGetCorePosition):\r
+ASM_FUNC(ArmPlatformGetCorePosition)\r
and x1, x0, #ARM_CORE_MASK\r
and x0, x0, #ARM_CLUSTER_MASK\r
add x0, x1, x0, LSR #6\r
#\r
\r
#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
#include <Library/ArmLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-#include "AsmMacroIoLib.inc"\r
\r
#include <Chipset/ArmCortexA9.h>\r
\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
-GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
-GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
-GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
-\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
-\r
-ASM_PFX(ArmPlatformPeiBootAction):\r
+ASM_FUNC(ArmPlatformPeiBootAction)\r
bx lr\r
\r
# IN None\r
# OUT r0 = SCU Base Address\r
-ASM_PFX(ArmGetScuBaseAddress):\r
+ASM_FUNC(ArmGetScuBaseAddress)\r
# Read Configuration Base Address Register. ArmCBar cannot be called to get\r
# the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
# offset 0x0000 from the Private Memory Region.\r
//ArmPlatformGetPrimaryCoreMpId (\r
// VOID\r
// );\r
-ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
- ldr r0, [r0]\r
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
+ MOV32 (r0, FixedPcdGet32 (PcdArmPrimaryCore))\r
bx lr\r
\r
# IN None\r
# OUT r0 = number of cores present in the system\r
-ASM_PFX(ArmGetCpuCountPerCluster):\r
+ASM_FUNC(ArmGetCpuCountPerCluster)\r
stmfd SP!, {r1-r2}\r
\r
# Read CP15 MIDR\r
\r
# Check if the CPU is A15\r
mov r1, r1, LSR #4\r
- LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r
+ MOV32 (r0, ARM_CPU_TYPE_MASK)\r
and r1, r1, r0\r
\r
- LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r
+ MOV32 (r0, ARM_CPU_TYPE_A15)\r
cmp r1, r0\r
beq _Read_cp15_reg\r
\r
//ArmPlatformIsPrimaryCore (\r
// IN UINTN MpId\r
// );\r
-ASM_PFX(ArmPlatformIsPrimaryCore):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
- ldr r1, [r1]\r
+ASM_FUNC(ArmPlatformIsPrimaryCore)\r
+ MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))\r
and r0, r0, r1\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
- ldr r1, [r1]\r
+ MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCore))\r
cmp r0, r1\r
moveq r0, #1\r
movne r0, #0\r
//ArmPlatformGetCorePosition (\r
// IN UINTN MpId\r
// );\r
-ASM_PFX(ArmPlatformGetCorePosition):\r
+ASM_FUNC(ArmPlatformGetCorePosition)\r
and r1, r0, #ARM_CORE_MASK\r
and r0, r0, #ARM_CLUSTER_MASK\r
add r0, r1, r0, LSR #7\r
//\r
\r
#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
#include <Library/ArmPlatformLib.h>\r
#include <Drivers/PL35xSmc.h>\r
#include <ArmPlatform.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
-GCC_ASM_IMPORT(PL35xSmcInitialize)\r
\r
//\r
// For each Chip Select: ChipSelect / SetCycle / SetOpMode\r
Note: This function must be implemented in assembler as there is no stack set up yet\r
\r
**/\r
-ASM_PFX(ArmPlatformSecBootAction):\r
+ASM_FUNC(ArmPlatformSecBootAction)\r
bx lr\r
\r
/**\r
pointer is not used (probably required to use assembly language)\r
\r
**/\r
-ASM_PFX(ArmPlatformSecBootMemoryInit):\r
+ASM_FUNC(ArmPlatformSecBootMemoryInit)\r
mov r5, lr\r
\r
//\r
// Initialize PL354 SMC\r
//\r
- LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
- LoadConstantToReg (VersatileExpressSmcConfiguration, r2)\r
- LoadConstantToReg (VersatileExpressSmcConfigurationEnd, r3)\r
+ MOV32 (r1, ARM_VE_SMC_CTRL_BASE)\r
+ MOV32 (r2, VersatileExpressSmcConfiguration)\r
+ MOV32 (r3, VersatileExpressSmcConfigurationEnd)\r
blx ASM_PFX(PL35xSmcInitialize)\r
\r
//\r
// Page mode setup for VRAM\r
//\r
- LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)\r
+ MOV32 (r2, VRAM_MOTHERBOARD_BASE)\r
\r
// Read current state\r
ldr r0, [r2, #0]\r
ldr r0, [r2, #0]\r
ldr r0, = 0x00000000\r
str r0, [r2, #0]\r
- LoadConstantToReg (0x00900090, r0)\r
+ ldr r0, = 0x00900090\r
str r0, [r2, #0]\r
\r
// Confirm page mode enabled\r