ArmPkg/ArmV7Mmu: make cached translation table accesses shareable

To align with the way normal cacheable memory is mapped, set the
shareable bit for cached accesses performed by the page table walker.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h
index 2545864775cf230464f714f7acc1ae49926e6115..f612154badc10a2d9e2e70a223da32f982108a94 100644 (file)
--- a/ArmPkg/Include/Chipset/ArmV7Mmu.h
+++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h
@@ -29,10 +29,10 @@
 #define TTBR_RGN_INNER_WRITE_THROUGH         BIT0\r
 #define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC   (BIT0|BIT6)\r
 \r
-#define TTBR_WRITE_THROUGH              ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH )\r
-#define TTBR_WRITE_BACK_NO_ALLOC        ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC )\r
+#define TTBR_WRITE_THROUGH              ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)\r
+#define TTBR_WRITE_BACK_NO_ALLOC        ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)\r
 #define TTBR_NON_CACHEABLE              ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )\r
-#define TTBR_WRITE_BACK_ALLOC           ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC )\r
+#define TTBR_WRITE_BACK_ALLOC           ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)\r
 \r
 \r
 #define TRANSLATION_TABLE_SECTION_COUNT                 4096\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index 8ed763cc8265c6948f9b8e6a8be5bd97b2f3e6ae..f03f609d21b2605dfba18c1ba5681c50c91cd830 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -265,6 +265,19 @@ ArmConfigureMmu (
     return RETURN_UNSUPPORTED;\r
   }\r
 \r
+  if (TTBRAttributes & TTBR_SHAREABLE) {\r
+    //\r
+    // Unlike the S bit in the short descriptors, which implies inner shareable\r
+    // on an implementation that supports two levels, the meaning of the S bit\r
+    // in the TTBR depends on the NOS bit, which defaults to Outer Shareable.\r
+    // However, we should only set this bit after we have confirmed that the\r
+    // implementation supports multiple levels, or else the NOS bit is UNK/SBZP\r
+    //\r
+    if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {\r
+      TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE;\r
+    }\r
+  }\r
+\r
   ArmCleanInvalidateDataCache ();\r
   ArmInvalidateInstructionCache ();\r
 \r