OvmfPkg: add and use industry standard macro PIIX4_PMBA_MASK

We already have the identical purpose (but different value) macro for
ICH9, namely ICH9_PMBASE_MASK in
"OvmfPkg/Include/IndustryStandard/Q35MchIch9.h".

Also, stop bit-negating signed integer constants.

Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Gabriel Somlo <somlo@cmu.edu>

diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
index 8cbd685ab50980ff31ee1ff4979458a3345763fe..baa4c063f16af84fdfa58b16f1c70fe6be462912 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
+++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
@@ -33,6 +33,8 @@
 #define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))\r
 \r
 #define PIIX4_PMBA             0x40\r
+#define PIIX4_PMBA_MASK          (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \\r
+                                  BIT10 | BIT9  | BIT8  | BIT7  | BIT6)\r
 \r
 #define PIIX4_PMREGMISC        0x80\r
 #define PIIX4_PMREGMISC_PMIOSE   BIT0\r

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index 109b267cf4aab1153cc1af1dd3ba9306da4e12ed..652545d8647e5e8d8c0fd702a910a51f5575f302 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -70,7 +70,7 @@ AcpiTimerLibConstructor (
     // If the Power Management Base Address is not programmed,\r
     // then program it now.\r
     //\r
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PIIX4_PMBA_VALUE);\r
+    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);\r
 \r
     //\r
     // Enable PMBA I/O port decodes\r

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index c46055a09b5200783f32b022f2422c47cc72140c..735dfd2e4bf90ff9e84e89002e9b99ed69ed48b5 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -68,7 +68,7 @@ AcpiTimerLibConstructor (
     // If the Power Management Base Address is not programmed,\r
     // then program it now.\r
     //\r
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PIIX4_PMBA_VALUE);\r
+    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);\r
 \r
     //\r
     // Enable PMBA I/O port decodes\r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 2348b56f0b2202827764637c6ac5413cc070444c..65b3df401abbf9d33269f9e77c08acaeeed01f98 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -412,7 +412,7 @@ MiscInitialization (
     // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
     // 1. set PMBA\r
     //\r
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PIIX4_PMBA_VALUE);\r
+    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);\r
 \r
     //\r
     // 2. set PCICMD/IOSE\r