UefiCpuPkg/CpuExceptionHandlerLib: Clear CET shadow stack token busy bit

If CET shadows stack feature enabled in SMM and stack switch is enabled.
When code execute from SMM handler to SMM exception, CPU will check SMM
exception shadow stack token busy bit if it is cleared or not.
If it is set, it will trigger #DF exception.
If it is not set, CPU will set the busy bit when enter SMM exception.
So, the busy bit should be cleared when return back form SMM exception to
SMM handler. Otherwise, keeping busy bit 1 will cause to trigger #DF
exception when enter SMM exception next time.
So, we use instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP to clear the
shadow stack token busy bit before RETF instruction in SMM exception.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Roger Feng <roger.feng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index 07b34c92a8922c5b6bb5e3b64c1c6f7e81fe4ea9..e7a81bebdb13e94840f983f5fe9099390a07d8d4 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -43,6 +43,9 @@
   gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize\r
 \r
+[FeaturePcd]\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard                    ## CONSUMES\r
+\r
 [Packages]\r
   MdePkg/MdePkg.dec\r
   MdeModulePkg/MdeModulePkg.dec\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
index feae7b3e06de4b393d2c5c37282761d41d899d54..cf5bfe40832b05aa35802e5c1e231bbf7f9b94db 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
@@ -57,3 +57,6 @@
 [Pcd]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard    # CONSUMES\r
 \r
+[FeaturePcd]\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard                    ## CONSUMES\r
+\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
index 967cb61ba6d9bb3df189756d851d22b1b8a8c8fb..8ae4feae62380b8371d67113da2df51d747a496b 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
@@ -49,3 +49,7 @@
   LocalApicLib\r
   PeCoffGetEntryPointLib\r
   VmgExitLib\r
+\r
+[FeaturePcd]\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard                    ## CONSUMES\r
+\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
index ea5b10b5c8e474c17fbad0c05187e39d25a42e11..c9f20da058606783c551c3a5c951c3a249f8cd74 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
@@ -53,3 +53,6 @@
   DebugLib\r
   VmgExitLib\r
 \r
+[FeaturePcd]\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard                    ## CONSUMES\r
+\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
index 26cae56cc5cf6b7608ce75197713a914a81a1780..ebe0eec874c3dd3d4ec80c4bc74b08496cbc966d 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
@@ -13,6 +13,7 @@
 ; Notes:\r
 ;\r
 ;------------------------------------------------------------------------------\r
+%include "Nasm.inc"\r
 \r
 ;\r
 ; CommonExceptionHandler()\r
@@ -23,6 +24,7 @@
 extern ASM_PFX(mErrorCodeFlag)    ; Error code flags for exceptions\r
 extern ASM_PFX(mDoFarReturnFlag)  ; Do far return flag\r
 extern ASM_PFX(CommonExceptionHandler)\r
+extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))\r
 \r
 SECTION .data\r
 \r
@@ -371,8 +373,48 @@ DoReturn:
     push    qword [rax + 0x18]       ; save EFLAGS in new location\r
     mov     rax, [rax]        ; restore rax\r
     popfq                     ; restore EFLAGS\r
-    DB      0x48               ; prefix to composite "retq" with next "retf"\r
-    retf                      ; far return\r
+\r
+    ; The follow algorithm is used for clear shadow stack token busy bit.\r
+    ; The comment is based on the sample shadow stack.\r
+    ; The sample shadow stack layout :\r
+    ; Address | Context\r
+    ;         +-------------------------+\r
+    ;  0xFD0  |   FREE                  | it is 0xFD8|0x02|(LMA & CS.L), after SAVEPREVSSP.\r
+    ;         +-------------------------+\r
+    ;  0xFD8  |  Prev SSP               |\r
+    ;         +-------------------------+\r
+    ;  0xFE0  |   RIP                   |\r
+    ;         +-------------------------+\r
+    ;  0xFE8  |   CS                    |\r
+    ;         +-------------------------+\r
+    ;  0xFF0  |  0xFF0 | BUSY           | BUSY flag cleared after CLRSSBSY\r
+    ;         +-------------------------+\r
+    ;  0xFF8  | 0xFD8|0x02|(LMA & CS.L) |\r
+    ;         +-------------------------+\r
+    ; Instructions for Intel Control Flow Enforcement Technology (CET) are supported since NASM version 2.15.01.\r
+    push     rax                ; SSP should be 0xFD8 at this point\r
+    cmp      byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r
+    jz       CetDone\r
+    mov      rax, cr4\r
+    and      rax, 0x800000      ; check if CET is enabled\r
+    jz       CetDone\r
+    mov      rax, 0x04          ; advance past cs:lip:prevssp;supervisor shadow stack token\r
+    INCSSP_RAX                  ; After this SSP should be 0xFF8\r
+    SAVEPREVSSP                 ; now the shadow stack restore token will be created at 0xFD0\r
+    READSSP_RAX                 ; Read new SSP, SSP should be 0x1000\r
+    push     rax\r
+    sub      rax, 0x10\r
+    CLRSSBSY_RAX                ; Clear token at 0xFF0, SSP should be 0 after this\r
+    sub      rax, 0x20\r
+    RSTORSSP_RAX                ; Restore to token at 0xFD0, new SSP will be 0xFD0\r
+    pop      rax\r
+    mov      rax, 0x01          ; Pop off the new save token created\r
+    INCSSP_RAX                  ; SSP should be 0xFD8 now\r
+CetDone:\r
+    pop      rax                ; restore rax\r
+\r
+    DB       0x48               ; prefix to composite "retq" with next "retf"\r
+    retf                        ; far return\r
 DoIret:\r
     iretq\r
 \r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf
index 743c2aa76684f0e46163839c6338d76d18610f63..a15f125d5b5e6f75e64633fa7c272ed882d7f8a2 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf
@@ -54,3 +54,7 @@
   LocalApicLib\r
   PeCoffGetEntryPointLib\r
   VmgExitLib\r
+\r
+[FeaturePcd]\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard                    ## CONSUMES\r
+\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
index 28f8e8e133e5cd8782ae40afc21deb49e7fe27eb..7ef3b1d48855f8e146f6e2cba5ab33ae0528eb98 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
@@ -173,6 +173,7 @@ InitShadowStack (
 {\r
   UINTN       SmmShadowStackSize;\r
   UINT64      *InterruptSspTable;\r
+  UINT32      InterruptSsp;\r
 \r
   if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r
     SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));\r
@@ -191,7 +192,19 @@ InitShadowStack (
         ASSERT (mSmmInterruptSspTables != 0);\r
         DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterruptSspTables));\r
       }\r
-      mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));\r
+\r
+      //\r
+      // The highest address on the stack (0xFF8) is a save-previous-ssp token pointing to a location that is 40 bytes away - 0xFD0.\r
+      // The supervisor shadow stack token is just above it at address 0xFF0. This is where the interrupt SSP table points.\r
+      // So when an interrupt of exception occurs, we can use SAVESSP/RESTORESSP/CLEARSSBUSY for the supervisor shadow stack,\r
+      // due to the reason the RETF in SMM exception handler cannot clear the BUSY flag with same CPL.\r
+      // (only IRET or RETF with different CPL can clear BUSY flag)\r
+      // Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime.\r
+      //\r
+      InterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));\r
+      *(UINT32 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;\r
+      mCetInterruptSsp = InterruptSsp - sizeof(UINT64);\r
+\r
       mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex);\r
       InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable;\r
       InterruptSspTable[1] = mCetInterruptSsp;\r