UefiCpuPkg: CpuDxe: Update GDT to be consistent with DxeIplPeim

The PiSmmCpuDxeSmm module makes some assumptions about GDT selectors
that are based on the GDT layout from the DxeIplPeim.  For example,
the protected mode entry code and (where appropriate) the long mode
entry code in the UefiCpuPkg/PiSmmCpuDxeSmm/*/MpFuncs.* assembly
files, which are used during S3 resume, open-code segment selector
values that depend on DxeIplPeim's GDT layout.

This updates the CpuDxe module to use the same GDT layout as the
DxeIplPeim.  This enables modules that are dispatched after
CpuDxe to find, and potentially save and restore, a GDT layout that
matches that of DxeIplPeim.  The DxeIplPeim has a 2 GDT entries for
data selectors that are identical.  These are LINEAR_SEL (GDT Offset
0x08)and LINEAR_DATA64_SEL (GDT offset 0x30).  LINEAL_SEL is used for
for IA32 DXE and the LINEAR_DATA64_SEL is used for X64 DXE. This
duplicate data selector was added to the CpuDxe module to keep the
GDT and all selectors consistent.

Using a consistent GDT also improves debug experience.

Reported-by: Laszlo Ersek <lersek@redhat.com>
Analyzed-by: Laszlo Ersek <lersek@redhat.com>
Link: http://article.gmane.org/gmane.comp.bios.edk2.devel/3568
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18710 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c
index 35a87a6e453e8bcf85a993df18c678d6c76c9978..9ef2fdfefbcb591eb69e52632374f19310af6b1a 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuGdt.c
+++ b/UefiCpuPkg/CpuDxe/CpuGdt.c
@@ -2,7 +2,7 @@
   C based implemention of IA32 interrupt handling only\r
   requiring a minimal assembly interrupt entry point.\r
 \r
   C based implemention of IA32 interrupt handling only\r
   requiring a minimal assembly interrupt entry point.\r
 \r

-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -35,10 +35,10 @@ STATIC GDT_ENTRIES GdtTemplate = {
   // LINEAR_SEL\r
   //\r
   {\r
   // LINEAR_SEL\r
   //\r
   {\r

-    0x0FFFF,        // limit 0xFFFFF\r
-    0x0,            // base 0\r
-    0x0,\r
-    0x092,          // present, ring 0, data, expand-up, writable\r
+    0x0FFFF,        // limit 15:0\r
+    0x0,            // base 15:0\r
+    0x0,            // base 23:16\r
+    0x092,          // present, ring 0, data, read/write\r

     0x0CF,          // page-granular, 32-bit\r
     0x0,\r
   },\r
     0x0CF,          // page-granular, 32-bit\r
     0x0,\r
   },\r


@@ -46,10 +46,10 @@ STATIC GDT_ENTRIES GdtTemplate = {
   // LINEAR_CODE_SEL\r
   //\r
   {\r
   // LINEAR_CODE_SEL\r
   //\r
   {\r

-    0x0FFFF,        // limit 0xFFFFF\r
-    0x0,            // base 0\r
-    0x0,\r
-    0x09A,          // present, ring 0, data, expand-up, writable\r
+    0x0FFFF,        // limit 15:0\r
+    0x0,            // base 15:0\r
+    0x0,            // base 23:16\r
+    0x09F,          // present, ring 0, code, execute/read, conforming, accessed\r

     0x0CF,          // page-granular, 32-bit\r
     0x0,\r
   },\r
     0x0CF,          // page-granular, 32-bit\r
     0x0,\r
   },\r


@@ -57,10 +57,10 @@ STATIC GDT_ENTRIES GdtTemplate = {
   // SYS_DATA_SEL\r
   //\r
   {\r
   // SYS_DATA_SEL\r
   //\r
   {\r

-    0x0FFFF,        // limit 0xFFFFF\r
-    0x0,            // base 0\r
-    0x0,\r
-    0x092,          // present, ring 0, data, expand-up, writable\r
+    0x0FFFF,        // limit 15:0\r
+    0x0,            // base 15:0\r
+    0x0,            // base 23:16\r
+    0x093,          // present, ring 0, data, read/write, accessed\r

     0x0CF,          // page-granular, 32-bit\r
     0x0,\r
   },\r
     0x0CF,          // page-granular, 32-bit\r
     0x0,\r
   },\r


@@ -68,45 +68,56 @@ STATIC GDT_ENTRIES GdtTemplate = {
   // SYS_CODE_SEL\r
   //\r
   {\r
   // SYS_CODE_SEL\r
   //\r
   {\r

-    0x0FFFF,        // limit 0xFFFFF\r
-    0x0,            // base 0\r
-    0x0,\r
-    0x09A,          // present, ring 0, data, expand-up, writable\r
+    0x0FFFF,        // limit 15:0\r
+    0x0,            // base 15:0\r
+    0x0,            // base 23:16\r
+    0x09A,          // present, ring 0, code, execute/read\r

     0x0CF,          // page-granular, 32-bit\r
     0x0,\r
   },\r
   //\r
     0x0CF,          // page-granular, 32-bit\r
     0x0,\r
   },\r
   //\r

-  // LINEAR_CODE64_SEL\r
+  // SPARE4_SEL\r

   //\r
   {\r
   //\r
   {\r

-    0x0FFFF,        // limit 0xFFFFF\r
-    0x0,            // base 0\r
-    0x0,\r
-    0x09B,          // present, ring 0, code, expand-up, writable\r
-    0x0AF,          // LimitHigh (CS.L=1, CS.D=0)\r
-    0x0,            // base (high)\r
+    0x0,            // limit 15:0\r
+    0x0,            // base 15:0\r
+    0x0,            // base 23:16\r
+    0x0,            // type\r
+    0x0,            // limit 19:16, flags\r
+    0x0,            // base 31:24\r

   },\r
   //\r
   },\r
   //\r

-  // SPARE4_SEL\r
+  // LINEAR_DATA64_SEL\r

   //\r
   {\r
   //\r
   {\r

-    0x0,            // limit 0\r
-    0x0,            // base 0\r
-    0x0,\r
-    0x0,            // present, ring 0, data, expand-up, writable\r
-    0x0,            // page-granular, 32-bit\r
+    0x0FFFF,        // limit 15:0\r
+    0x0,            // base 15:0\r
+    0x0,            // base 23:16\r
+    0x092,          // present, ring 0, data, read/write\r
+    0x0CF,          // page-granular, 32-bit\r

     0x0,\r
   },\r
   //\r
     0x0,\r
   },\r
   //\r

+  // LINEAR_CODE64_SEL\r
+  //\r
+  {\r
+    0x0FFFF,        // limit 15:0\r
+    0x0,            // base 15:0\r
+    0x0,            // base 23:16\r
+    0x09A,          // present, ring 0, code, execute/read\r
+    0x0AF,          // page-granular, 64-bit code\r
+    0x0,            // base (high)\r
+  },\r
+  //\r

   // SPARE5_SEL\r
   //\r
   {\r
   // SPARE5_SEL\r
   //\r
   {\r

-    0x0,            // limit 0\r
-    0x0,            // base 0\r
-    0x0,\r
-    0x0,            // present, ring 0, data, expand-up, writable\r
-    0x0,            // page-granular, 32-bit\r
-    0x0,\r
+    0x0,            // limit 15:0\r
+    0x0,            // base 15:0\r
+    0x0,            // base 23:16\r
+    0x0,            // type\r
+    0x0,            // limit 19:16, flags\r
+    0x0,            // base 31:24\r

   },\r
 };\r
 \r
   },\r
 };\r
 \r

diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h
index 7ecec5d5d9f7ba9f0923a52c81052b2a90b91383..2a007516024b7e9e03d8f379f6e5399f49c87c52 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuGdt.h
+++ b/UefiCpuPkg/CpuDxe/CpuGdt.h
@@ -2,7 +2,7 @@
   C based implemention of IA32 interrupt handling only\r
   requiring a minimal assembly interrupt entry point.\r
 \r
   C based implemention of IA32 interrupt handling only\r
   requiring a minimal assembly interrupt entry point.\r
 \r

-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -42,8 +42,9 @@ struct _GDT_ENTRIES {
   GDT_ENTRY LinearCode;\r
   GDT_ENTRY SysData;\r
   GDT_ENTRY SysCode;\r
   GDT_ENTRY LinearCode;\r
   GDT_ENTRY SysData;\r
   GDT_ENTRY SysCode;\r

-  GDT_ENTRY LinearCode64;\r

   GDT_ENTRY Spare4;\r
   GDT_ENTRY Spare4;\r

+  GDT_ENTRY LinearData64;\r
+  GDT_ENTRY LinearCode64;\r

   GDT_ENTRY Spare5;\r
 } GDT_ENTRIES;\r
 \r
   GDT_ENTRY Spare5;\r
 } GDT_ENTRIES;\r
 \r


@@ -54,8 +55,9 @@ struct _GDT_ENTRIES {
 #define LINEAR_CODE_SEL   OFFSET_OF (GDT_ENTRIES, LinearCode)\r
 #define SYS_DATA_SEL      OFFSET_OF (GDT_ENTRIES, SysData)\r
 #define SYS_CODE_SEL      OFFSET_OF (GDT_ENTRIES, SysCode)\r
 #define LINEAR_CODE_SEL   OFFSET_OF (GDT_ENTRIES, LinearCode)\r
 #define SYS_DATA_SEL      OFFSET_OF (GDT_ENTRIES, SysData)\r
 #define SYS_CODE_SEL      OFFSET_OF (GDT_ENTRIES, SysCode)\r

-#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)\r

 #define SPARE4_SEL        OFFSET_OF (GDT_ENTRIES, Spare4)\r
 #define SPARE4_SEL        OFFSET_OF (GDT_ENTRIES, Spare4)\r

+#define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64)\r
+#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)\r

 #define SPARE5_SEL        OFFSET_OF (GDT_ENTRIES, Spare5)\r
 \r
 #if defined (MDE_CPU_IA32)\r
 #define SPARE5_SEL        OFFSET_OF (GDT_ENTRIES, Spare5)\r
 \r
 #if defined (MDE_CPU_IA32)\r


@@ -63,7 +65,7 @@ struct _GDT_ENTRIES {
 #define CPU_DATA_SEL LINEAR_SEL\r
 #elif defined (MDE_CPU_X64)\r
 #define CPU_CODE_SEL LINEAR_CODE64_SEL\r
 #define CPU_DATA_SEL LINEAR_SEL\r
 #elif defined (MDE_CPU_X64)\r
 #define CPU_CODE_SEL LINEAR_CODE64_SEL\r

-#define CPU_DATA_SEL LINEAR_SEL\r
+#define CPU_DATA_SEL LINEAR_DATA64_SEL\r

 #else\r
 #error CPU type not supported for CPU GDT initialization!\r
 #endif\r
 #else\r
 #error CPU type not supported for CPU GDT initialization!\r
 #endif\r