ArmPkg/ArmExceptionLib: fold exception handler prologue into vector table

Unlike the AArch32 vector table, which has room for a single instruction
for each exception type, the AArch64 exception table has 128 byte slots,
which can easily hold the shared prologues that are emitted out of line.

So refactor this code into a single macro, and expand it into each vector
table slot. Since the address of the command handler entry point is no
longer patched in by the C code, we can just emit the literal into each
vector entry directly.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>

diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
index 790ce009b8dea170b278edcaf083c86df14bdac2..c47974b81e8b4142af2acc444bc228e819419482 100644 (file)
--- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
+++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
@@ -99,8 +99,6 @@
 */\r
 \r
 GCC_ASM_EXPORT(ExceptionHandlersEnd)\r
-GCC_ASM_EXPORT(CommonExceptionEntry)\r
-GCC_ASM_EXPORT(AsmCommonExceptionEntry)\r
 GCC_ASM_EXPORT(CommonCExceptionHandler)\r
 \r
 .text\r
@@ -172,142 +170,110 @@ ASM_PFX(ExceptionHandlersStart):
 VECTOR_BASE(ExceptionHandlersStart)\r
 #endif\r
 \r
+#undef  REG_PAIR\r
+#undef  REG_ONE\r
+#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE)  stp  REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]\r
+#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE)         stur REG1, [sp, #(OFFSET-CONTEXT_SIZE)]\r
+\r
+  .macro  ExceptionEntry, val\r
+  // Move the stackpointer so we can reach our structure with the str instruction.\r
+  sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
+\r
+  // Save all the General regs before touching x0 and x1.\r
+  // This does not save r31(SP) as it is special. We do that later.\r
+  ALL_GP_REGS\r
+\r
+  // Record the type of exception that occurred.\r
+  mov       x0, #\val\r
+\r
+  // Jump to our general handler to deal with all the common parts and process the exception.\r
+  ldr       x1, =ASM_PFX(CommonExceptionEntry)\r
+  br        x1\r
+  .ltorg\r
+  .endm\r
+\r
 //\r
 // Current EL with SP0 : 0x0 - 0x180\r
 //\r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SYNC)\r
 ASM_PFX(SynchronousExceptionSP0):\r
-  b   ASM_PFX(SynchronousExceptionEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_IRQ)\r
 ASM_PFX(IrqSP0):\r
-  b   ASM_PFX(IrqEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_IRQ\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_FIQ)\r
 ASM_PFX(FiqSP0):\r
-  b   ASM_PFX(FiqEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_FIQ\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SERR)\r
 ASM_PFX(SErrorSP0):\r
-  b   ASM_PFX(SErrorEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_SERROR\r
 \r
 //\r
 // Current EL with SPx: 0x200 - 0x380\r
 //\r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)\r
 ASM_PFX(SynchronousExceptionSPx):\r
-  b   ASM_PFX(SynchronousExceptionEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)\r
 ASM_PFX(IrqSPx):\r
-  b   ASM_PFX(IrqEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_IRQ\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)\r
 ASM_PFX(FiqSPx):\r
-  b   ASM_PFX(FiqEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_FIQ\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)\r
 ASM_PFX(SErrorSPx):\r
-  b   ASM_PFX(SErrorEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_SERROR\r
 \r
 //\r
 // Lower EL using AArch64 : 0x400 - 0x580\r
 //\r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SYNC)\r
 ASM_PFX(SynchronousExceptionA64):\r
-  b   ASM_PFX(SynchronousExceptionEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_IRQ)\r
 ASM_PFX(IrqA64):\r
-  b   ASM_PFX(IrqEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_IRQ\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_FIQ)\r
 ASM_PFX(FiqA64):\r
-  b   ASM_PFX(FiqEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_FIQ\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SERR)\r
 ASM_PFX(SErrorA64):\r
-  b   ASM_PFX(SErrorEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_SERROR\r
 \r
 //\r
 // Lower EL using AArch32 : 0x600 - 0x780\r
 //\r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SYNC)\r
 ASM_PFX(SynchronousExceptionA32):\r
-  b   ASM_PFX(SynchronousExceptionEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_IRQ)\r
 ASM_PFX(IrqA32):\r
-  b   ASM_PFX(IrqEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_IRQ\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_FIQ)\r
 ASM_PFX(FiqA32):\r
-  b   ASM_PFX(FiqEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_FIQ\r
 \r
 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SERR)\r
 ASM_PFX(SErrorA32):\r
-  b   ASM_PFX(SErrorEntry)\r
+  ExceptionEntry  EXCEPT_AARCH64_SERROR\r
 \r
 VECTOR_END(ExceptionHandlersStart)\r
 \r
-#undef  REG_PAIR\r
-#undef  REG_ONE\r
-#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE)  stp  REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]\r
-#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE)         stur REG1, [sp, #(OFFSET-CONTEXT_SIZE)]\r
-\r
-ASM_PFX(SynchronousExceptionEntry):\r
-  // Move the stackpointer so we can reach our structure with the str instruction.\r
-  sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
-\r
-  // Save all the General regs before touching x0 and x1.\r
-  // This does not save r31(SP) as it is special. We do that later.\r
-  ALL_GP_REGS\r
-\r
-  // Record the type of exception that occurred.\r
-  mov       x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
-\r
-  // Jump to our general handler to deal with all the common parts and process the exception.\r
-  ldr       x1, ASM_PFX(CommonExceptionEntry)\r
-  br        x1\r
-\r
-ASM_PFX(IrqEntry):\r
-  sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
-  ALL_GP_REGS\r
-  mov       x0, #EXCEPT_AARCH64_IRQ\r
-  ldr       x1, ASM_PFX(CommonExceptionEntry)\r
-  br        x1\r
-\r
-ASM_PFX(FiqEntry):\r
-  sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
-  ALL_GP_REGS\r
-  mov       x0, #EXCEPT_AARCH64_FIQ\r
-  ldr       x1, ASM_PFX(CommonExceptionEntry)\r
-  br        x1\r
-\r
-ASM_PFX(SErrorEntry):\r
-  sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)\r
-  ALL_GP_REGS\r
-  mov       x0, #EXCEPT_AARCH64_SERROR\r
-  ldr       x1, ASM_PFX(CommonExceptionEntry)\r
-  br        x1\r
-\r
-\r
-//\r
-// This gets patched by the C code that patches in the vector table\r
-//\r
-.align 3\r
-ASM_PFX(CommonExceptionEntry):\r
-  .8byte ASM_PFX(AsmCommonExceptionEntry)\r
-\r
 ASM_PFX(ExceptionHandlersEnd):\r
 \r
 \r
-\r
-//\r
-// This code runs from CpuDxe driver loaded address. It is patched into\r
-// CommonExceptionEntry.\r
-//\r
-ASM_PFX(AsmCommonExceptionEntry):\r
+ASM_PFX(CommonExceptionEntry):\r
   /* NOTE:\r
      We have to break up the save code because the immediate value to be used\r
      with the SP is too big to do it all in one step so we need to shuffle the SP\r