#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
#------------------------------------------------------------------------------\r
\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmReadCntFrq)\r
-GCC_ASM_EXPORT(ArmWriteCntFrq)\r
-GCC_ASM_EXPORT(ArmReadCntPct)\r
-GCC_ASM_EXPORT(ArmReadCntkCtl)\r
-GCC_ASM_EXPORT(ArmWriteCntkCtl)\r
-GCC_ASM_EXPORT(ArmReadCntpTval)\r
-GCC_ASM_EXPORT(ArmWriteCntpTval)\r
-GCC_ASM_EXPORT(ArmReadCntpCtl)\r
-GCC_ASM_EXPORT(ArmWriteCntpCtl)\r
-GCC_ASM_EXPORT(ArmReadCntvTval)\r
-GCC_ASM_EXPORT(ArmWriteCntvTval)\r
-GCC_ASM_EXPORT(ArmReadCntvCtl)\r
-GCC_ASM_EXPORT(ArmWriteCntvCtl)\r
-GCC_ASM_EXPORT(ArmReadCntvCt)\r
-GCC_ASM_EXPORT(ArmReadCntpCval)\r
-GCC_ASM_EXPORT(ArmWriteCntpCval)\r
-GCC_ASM_EXPORT(ArmReadCntvCval)\r
-GCC_ASM_EXPORT(ArmWriteCntvCval)\r
-GCC_ASM_EXPORT(ArmReadCntvOff)\r
-GCC_ASM_EXPORT(ArmWriteCntvOff)\r
-\r
-ASM_PFX(ArmReadCntFrq):\r
+#include <AsmMacroIoLibV8.h>\r
+\r
+ASM_FUNC(ArmReadCntFrq)\r
mrs x0, cntfrq_el0 // Read CNTFRQ\r
ret\r
\r
\r
# NOTE - Can only write while at highest implemented EL level (EL3 on model). Else ReadOnly (EL2, EL1, EL0)\r
-ASM_PFX(ArmWriteCntFrq):\r
+ASM_FUNC(ArmWriteCntFrq)\r
msr cntfrq_el0, x0 // Write to CNTFRQ\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntPct):\r
+ASM_FUNC(ArmReadCntPct)\r
mrs x0, cntpct_el0 // Read CNTPCT (Physical counter register)\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntkCtl):\r
+ASM_FUNC(ArmReadCntkCtl)\r
mrs x0, cntkctl_el1 // Read CNTK_CTL (Timer PL1 Control Register)\r
ret\r
\r
\r
-ASM_PFX(ArmWriteCntkCtl):\r
+ASM_FUNC(ArmWriteCntkCtl)\r
msr cntkctl_el1, x0 // Write to CNTK_CTL (Timer PL1 Control Register)\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntpTval):\r
+ASM_FUNC(ArmReadCntpTval)\r
mrs x0, cntp_tval_el0 // Read CNTP_TVAL (PL1 physical timer value register)\r
ret\r
\r
\r
-ASM_PFX(ArmWriteCntpTval):\r
+ASM_FUNC(ArmWriteCntpTval)\r
msr cntp_tval_el0, x0 // Write to CNTP_TVAL (PL1 physical timer value register)\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntpCtl):\r
+ASM_FUNC(ArmReadCntpCtl)\r
mrs x0, cntp_ctl_el0 // Read CNTP_CTL (PL1 Physical Timer Control Register)\r
ret\r
\r
\r
-ASM_PFX(ArmWriteCntpCtl):\r
+ASM_FUNC(ArmWriteCntpCtl)\r
msr cntp_ctl_el0, x0 // Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntvTval):\r
+ASM_FUNC(ArmReadCntvTval)\r
mrs x0, cntv_tval_el0 // Read CNTV_TVAL (Virtual Timer Value register)\r
ret\r
\r
\r
-ASM_PFX(ArmWriteCntvTval):\r
+ASM_FUNC(ArmWriteCntvTval)\r
msr cntv_tval_el0, x0 // Write to CNTV_TVAL (Virtual Timer Value register)\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntvCtl):\r
+ASM_FUNC(ArmReadCntvCtl)\r
mrs x0, cntv_ctl_el0 // Read CNTV_CTL (Virtual Timer Control Register)\r
ret\r
\r
\r
-ASM_PFX(ArmWriteCntvCtl):\r
+ASM_FUNC(ArmWriteCntvCtl)\r
msr cntv_ctl_el0, x0 // Write to CNTV_CTL (Virtual Timer Control Register)\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntvCt):\r
+ASM_FUNC(ArmReadCntvCt)\r
mrs x0, cntvct_el0 // Read CNTVCT (Virtual Count Register)\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntpCval):\r
+ASM_FUNC(ArmReadCntpCval)\r
mrs x0, cntp_cval_el0 // Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
ret\r
\r
\r
-ASM_PFX(ArmWriteCntpCval):\r
+ASM_FUNC(ArmWriteCntpCval)\r
msr cntp_cval_el0, x0 // Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntvCval):\r
+ASM_FUNC(ArmReadCntvCval)\r
mrs x0, cntv_cval_el0 // Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
ret\r
\r
\r
-ASM_PFX(ArmWriteCntvCval):\r
+ASM_FUNC(ArmWriteCntvCval)\r
msr cntv_cval_el0, x0 // write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
ret\r
\r
\r
-ASM_PFX(ArmReadCntvOff):\r
+ASM_FUNC(ArmReadCntvOff)\r
mrs x0, cntvoff_el2 // Read CNTVOFF (virtual Offset register)\r
ret\r
\r
\r
-ASM_PFX(ArmWriteCntvOff):\r
+ASM_FUNC(ArmWriteCntvOff)\r
msr cntvoff_el2, x0 // Write to CNTVOFF (Virtual Offset register)\r
ret\r
\r
#\r
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#include <Chipset/AArch64.h>\r
#include <AsmMacroIoLibV8.h>\r
\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT (ArmInvalidateInstructionCache)\r
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)\r
-GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)\r
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)\r
-GCC_ASM_EXPORT (ArmEnableMmu)\r
-GCC_ASM_EXPORT (ArmDisableMmu)\r
-GCC_ASM_EXPORT (ArmDisableCachesAndMmu)\r
-GCC_ASM_EXPORT (ArmMmuEnabled)\r
-GCC_ASM_EXPORT (ArmEnableDataCache)\r
-GCC_ASM_EXPORT (ArmDisableDataCache)\r
-GCC_ASM_EXPORT (ArmEnableInstructionCache)\r
-GCC_ASM_EXPORT (ArmDisableInstructionCache)\r
-GCC_ASM_EXPORT (ArmDisableAlignmentCheck)\r
-GCC_ASM_EXPORT (ArmEnableAlignmentCheck)\r
-GCC_ASM_EXPORT (ArmEnableBranchPrediction)\r
-GCC_ASM_EXPORT (ArmDisableBranchPrediction)\r
-GCC_ASM_EXPORT (AArch64AllDataCachesOperation)\r
-GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
-GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
-GCC_ASM_EXPORT (ArmWriteVBar)\r
-GCC_ASM_EXPORT (ArmReadVBar)\r
-GCC_ASM_EXPORT (ArmEnableVFP)\r
-GCC_ASM_EXPORT (ArmCallWFI)\r
-GCC_ASM_EXPORT (ArmReadMpidr)\r
-GCC_ASM_EXPORT (ArmReadTpidrurw)\r
-GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
-GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
-GCC_ASM_EXPORT (ArmReadIdPfr0)\r
-GCC_ASM_EXPORT (ArmReadIdPfr1)\r
-GCC_ASM_EXPORT (ArmWriteHcr)\r
-GCC_ASM_EXPORT (ArmReadHcr)\r
-GCC_ASM_EXPORT (ArmReadCurrentEL)\r
-GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntry)\r
-GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntrySize)\r
-\r
.set CTRL_M_BIT, (1 << 0)\r
.set CTRL_A_BIT, (1 << 1)\r
.set CTRL_C_BIT, (1 << 2)\r
.set CTRL_V_BIT, (1 << 12)\r
.set CPACR_VFP_BITS, (3 << 20)\r
\r
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
+ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)\r
dc ivac, x0 // Invalidate single data cache line\r
ret\r
\r
\r
-ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
+ASM_FUNC(ArmCleanDataCacheEntryByMVA)\r
dc cvac, x0 // Clean single data cache line\r
ret\r
\r
\r
-ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):\r
+ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)\r
dc cvau, x0 // Clean single data cache line to PoU\r
ret\r
\r
-ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):\r
+ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)\r
ic ivau, x0 // Invalidate single instruction cache line to PoU\r
ret\r
\r
\r
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
+ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)\r
dc civac, x0 // Clean and invalidate single data cache line\r
ret\r
\r
\r
-ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
+ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r
dc isw, x0 // Invalidate this line\r
ret\r
\r
\r
-ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
+ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r
dc cisw, x0 // Clean and Invalidate this line\r
ret\r
\r
\r
-ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
+ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r
dc csw, x0 // Clean this line\r
ret\r
\r
\r
-ASM_PFX(ArmInvalidateInstructionCache):\r
+ASM_FUNC(ArmInvalidateInstructionCache)\r
ic iallu // Invalidate entire instruction cache\r
dsb sy\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmEnableMmu):\r
+ASM_FUNC(ArmEnableMmu)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, sctlr_el1 // Read System control register EL1\r
b 4f\r
ret\r
\r
\r
-ASM_PFX(ArmDisableMmu):\r
+ASM_FUNC(ArmDisableMmu)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, sctlr_el1 // Read System Control Register EL1\r
b 4f\r
ret\r
\r
\r
-ASM_PFX(ArmDisableCachesAndMmu):\r
+ASM_FUNC(ArmDisableCachesAndMmu)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, sctlr_el1 // Get control register EL1\r
b 4f\r
ret\r
\r
\r
-ASM_PFX(ArmMmuEnabled):\r
+ASM_FUNC(ArmMmuEnabled)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, sctlr_el1 // Get control register EL1\r
b 4f\r
ret\r
\r
\r
-ASM_PFX(ArmEnableDataCache):\r
+ASM_FUNC(ArmEnableDataCache)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, sctlr_el1 // Get control register EL1\r
b 4f\r
ret\r
\r
\r
-ASM_PFX(ArmDisableDataCache):\r
+ASM_FUNC(ArmDisableDataCache)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, sctlr_el1 // Get control register EL1\r
b 4f\r
ret\r
\r
\r
-ASM_PFX(ArmEnableInstructionCache):\r
+ASM_FUNC(ArmEnableInstructionCache)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, sctlr_el1 // Get control register EL1\r
b 4f\r
ret\r
\r
\r
-ASM_PFX(ArmDisableInstructionCache):\r
+ASM_FUNC(ArmDisableInstructionCache)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, sctlr_el1 // Get control register EL1\r
b 4f\r
ret\r
\r
\r
-ASM_PFX(ArmEnableAlignmentCheck):\r
+ASM_FUNC(ArmEnableAlignmentCheck)\r
EL1_OR_EL2(x1)\r
1: mrs x0, sctlr_el1 // Get control register EL1\r
b 3f\r
ret\r
\r
\r
-ASM_PFX(ArmDisableAlignmentCheck):\r
+ASM_FUNC(ArmDisableAlignmentCheck)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, sctlr_el1 // Get control register EL1\r
b 4f\r
\r
\r
// Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now\r
-ASM_PFX(ArmEnableBranchPrediction):\r
+ASM_FUNC(ArmEnableBranchPrediction)\r
ret\r
\r
\r
// Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.\r
-ASM_PFX(ArmDisableBranchPrediction):\r
+ASM_FUNC(ArmDisableBranchPrediction)\r
ret\r
\r
\r
-ASM_PFX(AArch64AllDataCachesOperation):\r
+ASM_FUNC(AArch64AllDataCachesOperation)\r
// We can use regs 0-7 and 9-15 without having to save/restore.\r
// Save our link register on the stack. - The stack must always be quad-word aligned\r
str x30, [sp, #-16]!\r
ret\r
\r
\r
-ASM_PFX(ArmDataMemoryBarrier):\r
+ASM_FUNC(ArmDataMemoryBarrier)\r
dmb sy\r
ret\r
\r
\r
-ASM_PFX(ArmDataSynchronizationBarrier):\r
+ASM_FUNC(ArmDataSynchronizationBarrier)\r
dsb sy\r
ret\r
\r
\r
-ASM_PFX(ArmInstructionSynchronizationBarrier):\r
+ASM_FUNC(ArmInstructionSynchronizationBarrier)\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmWriteVBar):\r
+ASM_FUNC(ArmWriteVBar)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: msr vbar_el1, x0 // Set the Address of the EL1 Vector Table in the VBAR register\r
b 4f\r
4: isb\r
ret\r
\r
-ASM_PFX(ArmReadVBar):\r
+ASM_FUNC(ArmReadVBar)\r
EL1_OR_EL2_OR_EL3(x1)\r
1: mrs x0, vbar_el1 // Set the Address of the EL1 Vector Table in the VBAR register\r
ret\r
ret\r
\r
\r
-ASM_PFX(ArmEnableVFP):\r
+ASM_FUNC(ArmEnableVFP)\r
// Check whether floating-point is implemented in the processor.\r
mov x1, x30 // Save LR\r
bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0)\r
4:ret\r
\r
\r
-ASM_PFX(ArmCallWFI):\r
+ASM_FUNC(ArmCallWFI)\r
wfi\r
ret\r
\r
\r
-ASM_PFX(ArmReadMpidr):\r
+ASM_FUNC(ArmReadMpidr)\r
mrs x0, mpidr_el1 // read EL1 MPIDR\r
ret\r
\r
\r
// Keep old function names for C compatibilty for now. Change later?\r
-ASM_PFX(ArmReadTpidrurw):\r
+ASM_FUNC(ArmReadTpidrurw)\r
mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r
ret\r
\r
\r
// Keep old function names for C compatibilty for now. Change later?\r
-ASM_PFX(ArmWriteTpidrurw):\r
+ASM_FUNC(ArmWriteTpidrurw)\r
msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r
ret\r
\r
\r
// Arch timers are mandatory on AArch64\r
-ASM_PFX(ArmIsArchTimerImplemented):\r
+ASM_FUNC(ArmIsArchTimerImplemented)\r
mov x0, #1\r
ret\r
\r
\r
-ASM_PFX(ArmReadIdPfr0):\r
+ASM_FUNC(ArmReadIdPfr0)\r
mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register\r
ret\r
\r
// A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.\r
// See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c\r
// Not defined yet, but stick in here for now, should read all zeros.\r
-ASM_PFX(ArmReadIdPfr1):\r
+ASM_FUNC(ArmReadIdPfr1)\r
mrs x0, id_aa64pfr1_el1 // Read ID_PFR1 Register\r
ret\r
\r
// VOID ArmWriteHcr(UINTN Hcr)\r
-ASM_PFX(ArmWriteHcr):\r
+ASM_FUNC(ArmWriteHcr)\r
msr hcr_el2, x0 // Write the passed HCR value\r
ret\r
\r
// UINTN ArmReadHcr(VOID)\r
-ASM_PFX(ArmReadHcr):\r
+ASM_FUNC(ArmReadHcr)\r
mrs x0, hcr_el2\r
ret\r
\r
// UINTN ArmReadCurrentEL(VOID)\r
-ASM_PFX(ArmReadCurrentEL):\r
+ASM_FUNC(ArmReadCurrentEL)\r
mrs x0, CurrentEL\r
ret\r
\r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
#include <AsmMacroIoLibV8.h>\r
\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT (ArmIsMpCore)\r
-GCC_ASM_EXPORT (ArmEnableAsynchronousAbort)\r
-GCC_ASM_EXPORT (ArmDisableAsynchronousAbort)\r
-GCC_ASM_EXPORT (ArmEnableIrq)\r
-GCC_ASM_EXPORT (ArmDisableIrq)\r
-GCC_ASM_EXPORT (ArmEnableFiq)\r
-GCC_ASM_EXPORT (ArmDisableFiq)\r
-GCC_ASM_EXPORT (ArmEnableInterrupts)\r
-GCC_ASM_EXPORT (ArmDisableInterrupts)\r
-GCC_ASM_EXPORT (ArmDisableAllExceptions)\r
-GCC_ASM_EXPORT (ReadCCSIDR)\r
-GCC_ASM_EXPORT (ReadCLIDR)\r
-\r
-#------------------------------------------------------------------------------\r
-\r
.set MPIDR_U_BIT, (30)\r
.set MPIDR_U_MASK, (1 << MPIDR_U_BIT)\r
\r
.set DAIF_WR_ALL, (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)\r
\r
\r
-ASM_PFX(ArmIsMpCore):\r
+ASM_FUNC(ArmIsMpCore)\r
mrs x0, mpidr_el1 // Read EL1 Mutliprocessor Affinty Reg (MPIDR)\r
and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system\r
lsr x0, x0, #MPIDR_U_BIT\r
ret\r
\r
\r
-ASM_PFX(ArmEnableAsynchronousAbort):\r
+ASM_FUNC(ArmEnableAsynchronousAbort)\r
msr daifclr, #DAIF_WR_ABORT_BIT\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmDisableAsynchronousAbort):\r
+ASM_FUNC(ArmDisableAsynchronousAbort)\r
msr daifset, #DAIF_WR_ABORT_BIT\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmEnableIrq):\r
+ASM_FUNC(ArmEnableIrq)\r
msr daifclr, #DAIF_WR_IRQ_BIT\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmDisableIrq):\r
+ASM_FUNC(ArmDisableIrq)\r
msr daifset, #DAIF_WR_IRQ_BIT\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmEnableFiq):\r
+ASM_FUNC(ArmEnableFiq)\r
msr daifclr, #DAIF_WR_FIQ_BIT\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmDisableFiq):\r
+ASM_FUNC(ArmDisableFiq)\r
msr daifset, #DAIF_WR_FIQ_BIT\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmEnableInterrupts):\r
+ASM_FUNC(ArmEnableInterrupts)\r
msr daifclr, #DAIF_WR_INT_BITS\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmDisableInterrupts):\r
+ASM_FUNC(ArmDisableInterrupts)\r
msr daifset, #DAIF_WR_INT_BITS\r
isb\r
ret\r
\r
\r
-ASM_PFX(ArmDisableAllExceptions):\r
+ASM_FUNC(ArmDisableAllExceptions)\r
msr daifset, #DAIF_WR_ALL\r
isb\r
ret\r
// ReadCCSIDR (\r
// IN UINT32 CSSELR\r
// )\r
-ASM_PFX(ReadCCSIDR):\r
+ASM_FUNC(ReadCCSIDR)\r
msr csselr_el1, x0 // Write Cache Size Selection Register (CSSELR)\r
isb\r
mrs x0, ccsidr_el1 // Read current Cache Size ID Register (CCSIDR)\r
// ReadCLIDR (\r
// IN UINT32 CSSELR\r
// )\r
-ASM_PFX(ReadCLIDR):\r
+ASM_FUNC(ReadCLIDR)\r
mrs x0, clidr_el1 // Read Cache Level ID Register\r
ret\r
\r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
#include <AsmMacroIoLib.h>\r
\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmIsMpCore)\r
-GCC_ASM_EXPORT(ArmHasMpExtensions)\r
-GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)\r
-GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)\r
-GCC_ASM_EXPORT(ArmEnableIrq)\r
-GCC_ASM_EXPORT(ArmDisableIrq)\r
-GCC_ASM_EXPORT(ArmEnableFiq)\r
-GCC_ASM_EXPORT(ArmDisableFiq)\r
-GCC_ASM_EXPORT(ArmEnableInterrupts)\r
-GCC_ASM_EXPORT(ArmDisableInterrupts)\r
-GCC_ASM_EXPORT(ReadCCSIDR)\r
-GCC_ASM_EXPORT(ReadCLIDR)\r
-GCC_ASM_EXPORT(ArmReadNsacr)\r
-GCC_ASM_EXPORT(ArmWriteNsacr)\r
-\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_PFX(ArmIsMpCore):\r
+ASM_FUNC(ArmIsMpCore)\r
mrc p15,0,R0,c0,c0,5\r
// Get Multiprocessing extension (bit31) & U bit (bit30)\r
and R0, R0, #0xC0000000\r
movne R0, #0\r
bx LR\r
\r
-ASM_PFX(ArmEnableAsynchronousAbort):\r
+ASM_FUNC(ArmEnableAsynchronousAbort)\r
cpsie a\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmDisableAsynchronousAbort):\r
+ASM_FUNC(ArmDisableAsynchronousAbort)\r
cpsid a\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmEnableIrq):\r
+ASM_FUNC(ArmEnableIrq)\r
cpsie i\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmDisableIrq):\r
+ASM_FUNC(ArmDisableIrq)\r
cpsid i\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmEnableFiq):\r
+ASM_FUNC(ArmEnableFiq)\r
cpsie f\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmDisableFiq):\r
+ASM_FUNC(ArmDisableFiq)\r
cpsid f\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmEnableInterrupts):\r
+ASM_FUNC(ArmEnableInterrupts)\r
cpsie if\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmDisableInterrupts):\r
+ASM_FUNC(ArmDisableInterrupts)\r
cpsid if\r
isb\r
bx LR\r
// ReadCCSIDR (\r
// IN UINT32 CSSELR\r
// )\r
-ASM_PFX(ReadCCSIDR):\r
+ASM_FUNC(ReadCCSIDR)\r
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r
isb\r
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)\r
// ReadCLIDR (\r
// IN UINT32 CSSELR\r
// )\r
-ASM_PFX(ReadCLIDR):\r
+ASM_FUNC(ReadCLIDR)\r
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r
bx lr\r
\r
-ASM_PFX(ArmReadNsacr):\r
+ASM_FUNC(ArmReadNsacr)\r
mrc p15, 0, r0, c1, c1, 2\r
bx lr\r
\r
-ASM_PFX(ArmWriteNsacr):\r
+ASM_FUNC(ArmWriteNsacr)\r
mcr p15, 0, r0, c1, c1, 2\r
bx lr\r
\r
#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
#------------------------------------------------------------------------------\r
\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT (ArmReadCntFrq)\r
-GCC_ASM_EXPORT (ArmWriteCntFrq)\r
-GCC_ASM_EXPORT (ArmReadCntPct)\r
-GCC_ASM_EXPORT (ArmReadCntkCtl)\r
-GCC_ASM_EXPORT (ArmWriteCntkCtl)\r
-GCC_ASM_EXPORT (ArmReadCntpTval)\r
-GCC_ASM_EXPORT (ArmWriteCntpTval)\r
-GCC_ASM_EXPORT (ArmReadCntpCtl)\r
-GCC_ASM_EXPORT (ArmWriteCntpCtl)\r
-GCC_ASM_EXPORT (ArmReadCntvTval)\r
-GCC_ASM_EXPORT (ArmWriteCntvTval)\r
-GCC_ASM_EXPORT (ArmReadCntvCtl)\r
-GCC_ASM_EXPORT (ArmWriteCntvCtl)\r
-GCC_ASM_EXPORT (ArmReadCntvCt)\r
-GCC_ASM_EXPORT (ArmReadCntpCval)\r
-GCC_ASM_EXPORT (ArmWriteCntpCval)\r
-GCC_ASM_EXPORT (ArmReadCntvCval)\r
-GCC_ASM_EXPORT (ArmWriteCntvCval)\r
-GCC_ASM_EXPORT (ArmReadCntvOff)\r
-GCC_ASM_EXPORT (ArmWriteCntvOff)\r
-\r
-ASM_PFX(ArmReadCntFrq):\r
+#include <AsmMacroIoLib.h>\r
+\r
+ASM_FUNC(ArmReadCntFrq)\r
mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ\r
bx lr\r
\r
-ASM_PFX(ArmWriteCntFrq):\r
+ASM_FUNC(ArmWriteCntFrq)\r
mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ\r
bx lr\r
\r
-ASM_PFX(ArmReadCntPct):\r
+ASM_FUNC(ArmReadCntPct)\r
mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)\r
bx lr\r
\r
-ASM_PFX(ArmReadCntkCtl):\r
+ASM_FUNC(ArmReadCntkCtl)\r
mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)\r
bx lr\r
\r
-ASM_PFX(ArmWriteCntkCtl):\r
+ASM_FUNC(ArmWriteCntkCtl)\r
mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)\r
bx lr\r
\r
-ASM_PFX(ArmReadCntpTval):\r
+ASM_FUNC(ArmReadCntpTval)\r
mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)\r
bx lr\r
\r
-ASM_PFX(ArmWriteCntpTval):\r
+ASM_FUNC(ArmWriteCntpTval)\r
mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)\r
bx lr\r
\r
-ASM_PFX(ArmReadCntpCtl):\r
+ASM_FUNC(ArmReadCntpCtl)\r
mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)\r
bx lr\r
\r
-ASM_PFX(ArmWriteCntpCtl):\r
+ASM_FUNC(ArmWriteCntpCtl)\r
mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
bx lr\r
\r
-ASM_PFX(ArmReadCntvTval):\r
+ASM_FUNC(ArmReadCntvTval)\r
mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)\r
bx lr\r
\r
-ASM_PFX(ArmWriteCntvTval):\r
+ASM_FUNC(ArmWriteCntvTval)\r
mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)\r
bx lr\r
\r
-ASM_PFX(ArmReadCntvCtl):\r
+ASM_FUNC(ArmReadCntvCtl)\r
mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)\r
bx lr\r
\r
-ASM_PFX(ArmWriteCntvCtl):\r
+ASM_FUNC(ArmWriteCntvCtl)\r
mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)\r
bx lr\r
\r
-ASM_PFX(ArmReadCntvCt):\r
+ASM_FUNC(ArmReadCntvCt)\r
mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)\r
bx lr\r
\r
-ASM_PFX(ArmReadCntpCval):\r
+ASM_FUNC(ArmReadCntpCval)\r
mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
bx lr\r
\r
-ASM_PFX(ArmWriteCntpCval):\r
+ASM_FUNC(ArmWriteCntpCval)\r
mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
bx lr\r
\r
-ASM_PFX(ArmReadCntvCval):\r
+ASM_FUNC(ArmReadCntvCval)\r
mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
bx lr\r
\r
-ASM_PFX(ArmWriteCntvCval):\r
+ASM_FUNC(ArmWriteCntvCval)\r
mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
bx lr\r
\r
-ASM_PFX(ArmReadCntvOff):\r
+ASM_FUNC(ArmReadCntvOff)\r
mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)\r
bx lr\r
\r
-ASM_PFX(ArmWriteCntvOff):\r
+ASM_FUNC(ArmWriteCntvOff)\r
mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)\r
bx lr\r
\r
#\r
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
#------------------------------------------------------------------------------\r
\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT (ArmInvalidateInstructionCache)\r
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)\r
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)\r
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)\r
-GCC_ASM_EXPORT (ArmEnableMmu)\r
-GCC_ASM_EXPORT (ArmDisableMmu)\r
-GCC_ASM_EXPORT (ArmDisableCachesAndMmu)\r
-GCC_ASM_EXPORT (ArmMmuEnabled)\r
-GCC_ASM_EXPORT (ArmEnableDataCache)\r
-GCC_ASM_EXPORT (ArmDisableDataCache)\r
-GCC_ASM_EXPORT (ArmEnableInstructionCache)\r
-GCC_ASM_EXPORT (ArmDisableInstructionCache)\r
-GCC_ASM_EXPORT (ArmEnableSWPInstruction)\r
-GCC_ASM_EXPORT (ArmEnableBranchPrediction)\r
-GCC_ASM_EXPORT (ArmDisableBranchPrediction)\r
-GCC_ASM_EXPORT (ArmSetLowVectors)\r
-GCC_ASM_EXPORT (ArmSetHighVectors)\r
-GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)\r
-GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
-GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
-GCC_ASM_EXPORT (ArmReadVBar)\r
-GCC_ASM_EXPORT (ArmWriteVBar)\r
-GCC_ASM_EXPORT (ArmEnableVFP)\r
-GCC_ASM_EXPORT (ArmCallWFI)\r
-GCC_ASM_EXPORT (ArmReadCbar)\r
-GCC_ASM_EXPORT (ArmReadMpidr)\r
-GCC_ASM_EXPORT (ArmReadTpidrurw)\r
-GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
-GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
-GCC_ASM_EXPORT (ArmReadIdPfr1)\r
+#include <AsmMacroIoLib.h>\r
\r
.set DC_ON, (0x1<<2)\r
.set IC_ON, (0x1<<12)\r
.set CTRL_I_BIT, (1 << 12)\r
\r
\r
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
+ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)\r
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r
bx lr\r
\r
-ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
+ASM_FUNC(ArmCleanDataCacheEntryByMVA)\r
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r
bx lr\r
\r
\r
-ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):\r
+ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)\r
mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU\r
bx lr\r
\r
-ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):\r
+ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)\r
mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU\r
mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor\r
bx lr\r
\r
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
+ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)\r
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r
bx lr\r
\r
\r
-ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
+ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r
mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\r
bx lr\r
\r
\r
-ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
+ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r
mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\r
bx lr\r
\r
\r
-ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
+ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r
mcr p15, 0, r0, c7, c10, 2 @ Clean this line\r
bx lr\r
\r
-ASM_PFX(ArmInvalidateInstructionCache):\r
+ASM_FUNC(ArmInvalidateInstructionCache)\r
mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache\r
dsb\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmEnableMmu):\r
+ASM_FUNC(ArmEnableMmu)\r
mrc p15,0,R0,c1,c0,0\r
orr R0,R0,#1\r
mcr p15,0,R0,c1,c0,0\r
bx LR\r
\r
\r
-ASM_PFX(ArmDisableMmu):\r
+ASM_FUNC(ArmDisableMmu)\r
mrc p15,0,R0,c1,c0,0\r
bic R0,R0,#1\r
mcr p15,0,R0,c1,c0,0 @Disable MMU\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmDisableCachesAndMmu):\r
+ASM_FUNC(ArmDisableCachesAndMmu)\r
mrc p15, 0, r0, c1, c0, 0 @ Get control register\r
bic r0, r0, #CTRL_M_BIT @ Disable MMU\r
bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmMmuEnabled):\r
+ASM_FUNC(ArmMmuEnabled)\r
mrc p15,0,R0,c1,c0,0\r
and R0,R0,#1\r
bx LR\r
\r
-ASM_PFX(ArmEnableDataCache):\r
+ASM_FUNC(ArmEnableDataCache)\r
ldr R1,=DC_ON\r
mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
orr R0,R0,R1 @Set C bit\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmDisableDataCache):\r
+ASM_FUNC(ArmDisableDataCache)\r
ldr R1,=DC_ON\r
mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
bic R0,R0,R1 @Clear C bit\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmEnableInstructionCache):\r
+ASM_FUNC(ArmEnableInstructionCache)\r
ldr R1,=IC_ON\r
mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
orr R0,R0,R1 @Set I bit\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmDisableInstructionCache):\r
+ASM_FUNC(ArmDisableInstructionCache)\r
ldr R1,=IC_ON\r
mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
bic R0,R0,R1 @Clear I bit.\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmEnableSWPInstruction):\r
+ASM_FUNC(ArmEnableSWPInstruction)\r
mrc p15, 0, r0, c1, c0, 0\r
orr r0, r0, #0x00000400\r
mcr p15, 0, r0, c1, c0, 0\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmEnableBranchPrediction):\r
+ASM_FUNC(ArmEnableBranchPrediction)\r
mrc p15, 0, r0, c1, c0, 0\r
orr r0, r0, #0x00000800\r
mcr p15, 0, r0, c1, c0, 0\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmDisableBranchPrediction):\r
+ASM_FUNC(ArmDisableBranchPrediction)\r
mrc p15, 0, r0, c1, c0, 0\r
bic r0, r0, #0x00000800\r
mcr p15, 0, r0, c1, c0, 0\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmSetLowVectors):\r
+ASM_FUNC(ArmSetLowVectors)\r
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
bic r0, r0, #0x00002000 @ clear V bit\r
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmSetHighVectors):\r
+ASM_FUNC(ArmSetHighVectors)\r
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
orr r0, r0, #0x00002000 @ Set V bit\r
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmV7AllDataCachesOperation):\r
+ASM_FUNC(ArmV7AllDataCachesOperation)\r
stmfd SP!,{r4-r12, LR}\r
mov R1, R0 @ Save Function call in R1\r
mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR\r
ldmfd SP!, {r4-r12, lr}\r
bx LR\r
\r
-ASM_PFX(ArmDataMemoryBarrier):\r
+ASM_FUNC(ArmDataMemoryBarrier)\r
dmb\r
bx LR\r
\r
-ASM_PFX(ArmDataSynchronizationBarrier):\r
+ASM_FUNC(ArmDataSynchronizationBarrier)\r
dsb\r
bx LR\r
\r
-ASM_PFX(ArmInstructionSynchronizationBarrier):\r
+ASM_FUNC(ArmInstructionSynchronizationBarrier)\r
isb\r
bx LR\r
\r
-ASM_PFX(ArmReadVBar):\r
+ASM_FUNC(ArmReadVBar)\r
# Set the Address of the Vector Table in the VBAR register\r
mrc p15, 0, r0, c12, c0, 0\r
bx lr\r
\r
-ASM_PFX(ArmWriteVBar):\r
+ASM_FUNC(ArmWriteVBar)\r
# Set the Address of the Vector Table in the VBAR register\r
mcr p15, 0, r0, c12, c0, 0\r
# Ensure the SCTLR.V bit is clear\r
isb\r
bx lr\r
\r
-ASM_PFX(ArmEnableVFP):\r
+ASM_FUNC(ArmEnableVFP)\r
# Read CPACR (Coprocessor Access Control Register)\r
mrc p15, 0, r0, c1, c0, 2\r
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
#endif\r
bx lr\r
\r
-ASM_PFX(ArmCallWFI):\r
+ASM_FUNC(ArmCallWFI)\r
wfi\r
bx lr\r
\r
#Note: Return 0 in Uniprocessor implementation\r
-ASM_PFX(ArmReadCbar):\r
+ASM_FUNC(ArmReadCbar)\r
mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register\r
bx lr\r
\r
-ASM_PFX(ArmReadMpidr):\r
+ASM_FUNC(ArmReadMpidr)\r
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
bx lr\r
\r
-ASM_PFX(ArmReadTpidrurw):\r
+ASM_FUNC(ArmReadTpidrurw)\r
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r
bx lr\r
\r
-ASM_PFX(ArmWriteTpidrurw):\r
+ASM_FUNC(ArmWriteTpidrurw)\r
mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW\r
bx lr\r
\r
-ASM_PFX(ArmIsArchTimerImplemented):\r
+ASM_FUNC(ArmIsArchTimerImplemented)\r
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1\r
and r0, r0, #0x000F0000\r
bx lr\r
\r
-ASM_PFX(ArmReadIdPfr1):\r
+ASM_FUNC(ArmReadIdPfr1)\r
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register\r
bx lr\r
\r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
#include <AsmMacroIoLibV8.h>\r
\r
-.text\r
-.align 3\r
-GCC_ASM_EXPORT (ArmReadMidr)\r
-GCC_ASM_EXPORT (ArmCacheInfo)\r
-GCC_ASM_EXPORT (ArmGetInterruptState)\r
-GCC_ASM_EXPORT (ArmGetFiqState)\r
-GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)\r
-GCC_ASM_EXPORT (ArmSetTTBR0)\r
-GCC_ASM_EXPORT (ArmGetTCR)\r
-GCC_ASM_EXPORT (ArmSetTCR)\r
-GCC_ASM_EXPORT (ArmGetMAIR)\r
-GCC_ASM_EXPORT (ArmSetMAIR)\r
-GCC_ASM_EXPORT (ArmWriteCpacr)\r
-GCC_ASM_EXPORT (ArmWriteAuxCr)\r
-GCC_ASM_EXPORT (ArmReadAuxCr)\r
-GCC_ASM_EXPORT (ArmInvalidateTlb)\r
-GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)\r
-GCC_ASM_EXPORT (ArmWriteCptr)\r
-GCC_ASM_EXPORT (ArmWriteScr)\r
-GCC_ASM_EXPORT (ArmWriteMVBar)\r
-GCC_ASM_EXPORT (ArmCallWFE)\r
-GCC_ASM_EXPORT (ArmCallSEV)\r
-GCC_ASM_EXPORT (ArmReadCpuActlr)\r
-GCC_ASM_EXPORT (ArmWriteCpuActlr)\r
-GCC_ASM_EXPORT (ArmReadSctlr)\r
-\r
-#------------------------------------------------------------------------------\r
-\r
.set DAIF_RD_FIQ_BIT, (1 << 6)\r
.set DAIF_RD_IRQ_BIT, (1 << 7)\r
\r
-ASM_PFX(ArmReadMidr):\r
+ASM_FUNC(ArmReadMidr)\r
mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r
ret\r
\r
-ASM_PFX(ArmCacheInfo):\r
+ASM_FUNC(ArmCacheInfo)\r
mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)\r
ret\r
\r
-ASM_PFX(ArmGetInterruptState):\r
+ASM_FUNC(ArmGetInterruptState)\r
mrs x0, daif\r
tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)\r
cset w0, eq // if Z=1 return 1, else 0\r
ret\r
\r
-ASM_PFX(ArmGetFiqState):\r
+ASM_FUNC(ArmGetFiqState)\r
mrs x0, daif\r
tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)\r
cset w0, eq // if Z=1 return 1, else 0\r
ret\r
\r
-ASM_PFX(ArmWriteCpacr):\r
+ASM_FUNC(ArmWriteCpacr)\r
msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)\r
ret\r
\r
-ASM_PFX(ArmWriteAuxCr):\r
+ASM_FUNC(ArmWriteAuxCr)\r
EL1_OR_EL2(x1)\r
1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
ret\r
2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
ret\r
\r
-ASM_PFX(ArmReadAuxCr):\r
+ASM_FUNC(ArmReadAuxCr)\r
EL1_OR_EL2(x1)\r
1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
ret\r
2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r
ret\r
\r
-ASM_PFX(ArmSetTTBR0):\r
+ASM_FUNC(ArmSetTTBR0)\r
EL1_OR_EL2_OR_EL3(x1)\r
1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)\r
b 4f\r
4:isb\r
ret\r
\r
-ASM_PFX(ArmGetTTBR0BaseAddress):\r
+ASM_FUNC(ArmGetTTBR0BaseAddress)\r
EL1_OR_EL2(x1)\r
1:mrs x0, ttbr0_el1\r
b 3f\r
2:mrs x0, ttbr0_el2\r
-3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */\r
- and x0, x0, x1\r
+3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */\r
isb\r
ret\r
\r
-ASM_PFX(ArmGetTCR):\r
+ASM_FUNC(ArmGetTCR)\r
EL1_OR_EL2_OR_EL3(x1)\r
1:mrs x0, tcr_el1\r
b 4f\r
4:isb\r
ret\r
\r
-ASM_PFX(ArmSetTCR):\r
+ASM_FUNC(ArmSetTCR)\r
EL1_OR_EL2_OR_EL3(x1)\r
1:msr tcr_el1, x0\r
b 4f\r
4:isb\r
ret\r
\r
-ASM_PFX(ArmGetMAIR):\r
+ASM_FUNC(ArmGetMAIR)\r
EL1_OR_EL2_OR_EL3(x1)\r
1:mrs x0, mair_el1\r
b 4f\r
4:isb\r
ret\r
\r
-ASM_PFX(ArmSetMAIR):\r
+ASM_FUNC(ArmSetMAIR)\r
EL1_OR_EL2_OR_EL3(x1)\r
1:msr mair_el1, x0\r
b 4f\r
// IN VOID *TranslationTableEntry // X0\r
// IN VOID *MVA // X1\r
// );\r
-ASM_PFX(ArmUpdateTranslationTableEntry):\r
+ASM_FUNC(ArmUpdateTranslationTableEntry)\r
dc civac, x0 // Clean and invalidate data line\r
dsb sy\r
EL1_OR_EL2_OR_EL3(x0)\r
isb\r
ret\r
\r
-ASM_PFX(ArmInvalidateTlb):\r
+ASM_FUNC(ArmInvalidateTlb)\r
EL1_OR_EL2_OR_EL3(x0)\r
1: tlbi vmalle1\r
b 4f\r
isb\r
ret\r
\r
-ASM_PFX(ArmWriteCptr):\r
+ASM_FUNC(ArmWriteCptr)\r
msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)\r
ret\r
\r
-ASM_PFX(ArmWriteScr):\r
+ASM_FUNC(ArmWriteScr)\r
msr scr_el3, x0 // Secure configuration register EL3\r
isb\r
ret\r
\r
-ASM_PFX(ArmWriteMVBar):\r
+ASM_FUNC(ArmWriteMVBar)\r
msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3\r
ret\r
\r
-ASM_PFX(ArmCallWFE):\r
+ASM_FUNC(ArmCallWFE)\r
wfe\r
ret\r
\r
-ASM_PFX(ArmCallSEV):\r
+ASM_FUNC(ArmCallSEV)\r
sev\r
ret\r
\r
-ASM_PFX(ArmReadCpuActlr):\r
+ASM_FUNC(ArmReadCpuActlr)\r
mrs x0, S3_1_c15_c2_0\r
ret\r
\r
-ASM_PFX(ArmWriteCpuActlr):\r
+ASM_FUNC(ArmWriteCpuActlr)\r
msr S3_1_c15_c2_0, x0\r
dsb sy\r
isb\r
ret\r
\r
-ASM_PFX(ArmReadSctlr):\r
+ASM_FUNC(ArmReadSctlr)\r
EL1_OR_EL2_OR_EL3(x1)\r
1:mrs x0, sctlr_el1\r
ret\r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
+# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
#include <AsmMacroIoLib.h>\r
\r
-.text\r
-.align 2\r
-GCC_ASM_EXPORT(ArmReadMidr)\r
-GCC_ASM_EXPORT(ArmCacheInfo)\r
-GCC_ASM_EXPORT(ArmGetInterruptState)\r
-GCC_ASM_EXPORT(ArmGetFiqState)\r
-GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)\r
-GCC_ASM_EXPORT(ArmSetTTBR0)\r
-GCC_ASM_EXPORT(ArmSetTTBCR)\r
-GCC_ASM_EXPORT(ArmSetDomainAccessControl)\r
-GCC_ASM_EXPORT(CPSRMaskInsert)\r
-GCC_ASM_EXPORT(CPSRRead)\r
-GCC_ASM_EXPORT(ArmReadCpacr)\r
-GCC_ASM_EXPORT(ArmWriteCpacr)\r
-GCC_ASM_EXPORT(ArmWriteAuxCr)\r
-GCC_ASM_EXPORT(ArmReadAuxCr)\r
-GCC_ASM_EXPORT(ArmInvalidateTlb)\r
-GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
-GCC_ASM_EXPORT(ArmReadScr)\r
-GCC_ASM_EXPORT(ArmWriteScr)\r
-GCC_ASM_EXPORT(ArmReadMVBar)\r
-GCC_ASM_EXPORT(ArmWriteMVBar)\r
-GCC_ASM_EXPORT(ArmReadHVBar)\r
-GCC_ASM_EXPORT(ArmWriteHVBar)\r
-GCC_ASM_EXPORT(ArmCallWFE)\r
-GCC_ASM_EXPORT(ArmCallSEV)\r
-GCC_ASM_EXPORT(ArmReadSctlr)\r
-GCC_ASM_EXPORT(ArmReadCpuActlr)\r
-GCC_ASM_EXPORT(ArmWriteCpuActlr)\r
-\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_PFX(ArmReadMidr):\r
+ASM_FUNC(ArmReadMidr)\r
mrc p15,0,R0,c0,c0,0\r
bx LR\r
\r
-ASM_PFX(ArmCacheInfo):\r
+ASM_FUNC(ArmCacheInfo)\r
mrc p15,0,R0,c0,c0,1\r
bx LR\r
\r
-ASM_PFX(ArmGetInterruptState):\r
+ASM_FUNC(ArmGetInterruptState)\r
mrs R0,CPSR\r
tst R0,#0x80 @Check if IRQ is enabled.\r
moveq R0,#1\r
movne R0,#0\r
bx LR\r
\r
-ASM_PFX(ArmGetFiqState):\r
+ASM_FUNC(ArmGetFiqState)\r
mrs R0,CPSR\r
tst R0,#0x40 @Check if FIQ is enabled.\r
moveq R0,#1\r
movne R0,#0\r
bx LR\r
\r
-ASM_PFX(ArmSetDomainAccessControl):\r
+ASM_FUNC(ArmSetDomainAccessControl)\r
mcr p15,0,r0,c3,c0,0\r
bx lr\r
\r
-ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert\r
+ASM_FUNC(CPSRMaskInsert) @ on entry, r0 is the mask and r1 is the field to insert\r
stmfd sp!, {r4-r12, lr} @ save all the banked registers\r
mov r3, sp @ copy the stack pointer into a non-banked register\r
mrs r2, cpsr @ read the cpsr\r
ldmfd sp!, {r4-r12, lr} @ restore registers\r
bx lr @ return (hopefully thumb-safe!)\r
\r
-ASM_PFX(CPSRRead):\r
+ASM_FUNC(CPSRRead)\r
mrs r0, cpsr\r
bx lr\r
\r
-ASM_PFX(ArmReadCpacr):\r
+ASM_FUNC(ArmReadCpacr)\r
mrc p15, 0, r0, c1, c0, 2\r
bx lr\r
\r
-ASM_PFX(ArmWriteCpacr):\r
+ASM_FUNC(ArmWriteCpacr)\r
mcr p15, 0, r0, c1, c0, 2\r
isb\r
bx lr\r
\r
-ASM_PFX(ArmWriteAuxCr):\r
+ASM_FUNC(ArmWriteAuxCr)\r
mcr p15, 0, r0, c1, c0, 1\r
bx lr\r
\r
-ASM_PFX(ArmReadAuxCr):\r
+ASM_FUNC(ArmReadAuxCr)\r
mrc p15, 0, r0, c1, c0, 1\r
bx lr\r
\r
-ASM_PFX(ArmSetTTBR0):\r
+ASM_FUNC(ArmSetTTBR0)\r
mcr p15,0,r0,c2,c0,0\r
isb\r
bx lr\r
\r
-ASM_PFX(ArmSetTTBCR):\r
+ASM_FUNC(ArmSetTTBCR)\r
mcr p15, 0, r0, c2, c0, 2\r
isb\r
bx lr\r
\r
-ASM_PFX(ArmGetTTBR0BaseAddress):\r
+ASM_FUNC(ArmGetTTBR0BaseAddress)\r
mrc p15,0,r0,c2,c0,0\r
- LoadConstantToReg(0xFFFFC000, r1)\r
+ MOV32 (r1, 0xFFFFC000)\r
and r0, r0, r1\r
isb\r
bx lr\r
// IN VOID *TranslationTableEntry // R0\r
// IN VOID *MVA // R1\r
// );\r
-ASM_PFX(ArmUpdateTranslationTableEntry):\r
+ASM_FUNC(ArmUpdateTranslationTableEntry)\r
mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA\r
dsb\r
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA\r
isb\r
bx lr\r
\r
-ASM_PFX(ArmInvalidateTlb):\r
+ASM_FUNC(ArmInvalidateTlb)\r
mov r0,#0\r
mcr p15,0,r0,c8,c7,0\r
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
isb\r
bx lr\r
\r
-ASM_PFX(ArmReadScr):\r
+ASM_FUNC(ArmReadScr)\r
mrc p15, 0, r0, c1, c1, 0\r
bx lr\r
\r
-ASM_PFX(ArmWriteScr):\r
+ASM_FUNC(ArmWriteScr)\r
mcr p15, 0, r0, c1, c1, 0\r
isb\r
bx lr\r
\r
-ASM_PFX(ArmReadHVBar):\r
+ASM_FUNC(ArmReadHVBar)\r
mrc p15, 4, r0, c12, c0, 0\r
bx lr\r
\r
-ASM_PFX(ArmWriteHVBar):\r
+ASM_FUNC(ArmWriteHVBar)\r
mcr p15, 4, r0, c12, c0, 0\r
bx lr\r
\r
-ASM_PFX(ArmReadMVBar):\r
+ASM_FUNC(ArmReadMVBar)\r
mrc p15, 0, r0, c12, c0, 1\r
bx lr\r
\r
-ASM_PFX(ArmWriteMVBar):\r
+ASM_FUNC(ArmWriteMVBar)\r
mcr p15, 0, r0, c12, c0, 1\r
bx lr\r
\r
-ASM_PFX(ArmCallWFE):\r
+ASM_FUNC(ArmCallWFE)\r
wfe\r
bx lr\r
\r
-ASM_PFX(ArmCallSEV):\r
+ASM_FUNC(ArmCallSEV)\r
sev\r
bx lr\r
\r
-ASM_PFX(ArmReadSctlr):\r
+ASM_FUNC(ArmReadSctlr)\r
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
bx lr\r
\r
-ASM_PFX(ArmReadCpuActlr):\r
+ASM_FUNC(ArmReadCpuActlr)\r
mrc p15, 0, r0, c1, c0, 1\r
bx lr\r
\r
-ASM_PFX(ArmWriteCpuActlr):\r
+ASM_FUNC(ArmWriteCpuActlr)\r
mcr p15, 0, r0, c1, c0, 1\r
dsb\r
isb\r
//\r
//------------------------------------------------------------------------------\r
\r
-#include <AsmMacroIoLib.h>\r
-\r
INCLUDE AsmMacroIoLib.inc\r
\r
\r
\r
RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r
mrc p15,0,r0,c2,c0,0\r
- LoadConstantToReg(0xFFFFC000, r1)\r
+ MOV32 r1, 0xFFFFC000\r
and r0, r0, r1\r
isb\r
bx lr\r
projects / mirror_edk2.git / commitdiff