\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Appendix A VMX Capability Reporting Facility, Section A.1.\r
+ September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Appendix A VMX Capability Reporting Facility, Section A.6.\r
+ September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.\r
\r
**/\r
\r
#define __ARCHITECTURAL_MSR_H__\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
+ See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
\r
@param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
+ See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
\r
@param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /\r
+ See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /\r
Display Model 05_01H.\r
\r
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r
/// 6] is set. If CPUID.01H:ECX[6] = 1.\r
///\r
UINT32 SenterGlobalEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r
+ /// enable runtime reconfiguration of SGX Launch Control via\r
+ /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r
+ ///\r
+ UINT32 SgxLaunchControlEnable:1;\r
///\r
/// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r
- /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is\r
- /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
+ /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
///\r
UINT32 SgxEnable:1;\r
UINT32 Reserved3:1;\r
} MSR_IA32_BIOS_SIGN_ID_REGISTER;\r
\r
\r
+/**\r
+ IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r
+ SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r
+ default value is the digest of Intel's signing key. Read permitted If\r
+ CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r
+ EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r
+\r
+ @param ECX MSR_IA32_SGXLEPUBKEYHASHn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r
+ AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r
+ @endcode\r
+ @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r
+/// @}\r
+\r
+\r
/**\r
SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
1.\r
\r
/**\r
Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r
- Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.\r
+ Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r
\r
@param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r
@param EAX Lower 32-bits of MSR value.\r
UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r
///\r
/// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r
- /// values for target duty cycle modulation.\r
+ /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 OnDemandClockModulationDutyCycle:3;\r
///\r
/// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 OnDemandClockModulationEnable:1;\r
UINT32 Reserved1:27;\r
Thermal Interrupt Control (R/W) Enables and disables the generation of an\r
interrupt on temperature transitions detected with the processor's thermal\r
sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r
- Introduced at Display Family / Display Model 0F_0H.\r
+ If CPUID.01H:EDX[22] = 1\r
\r
@param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bit 0] High-Temperature Interrupt Enable.\r
+ /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 HighTempEnable:1;\r
///\r
- /// [Bit 1] Low-Temperature Interrupt Enable.\r
+ /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 LowTempEnable:1;\r
///\r
- /// [Bit 2] PROCHOT# Interrupt Enable.\r
+ /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_Enable:1;\r
///\r
- /// [Bit 3] FORCEPR# Interrupt Enable.\r
+ /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 FORCEPR_Enable:1;\r
///\r
/// [Bit 4] Critical Temperature Interrupt Enable.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempEnable:1;\r
UINT32 Reserved1:3;\r
///\r
- /// [Bits 14:8] Threshold #1 Value.\r
+ /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold1:7;\r
///\r
- /// [Bit 15] Threshold #1 Interrupt Enable.\r
+ /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold1Enable:1;\r
///\r
- /// [Bits 22:16] Threshold #2 Value.\r
+ /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold2:7;\r
///\r
- /// [Bit 23] Threshold #2 Interrupt Enable.\r
+ /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold2Enable:1;\r
///\r
/**\r
Thermal Status Information (RO) Contains status information about the\r
processor's thermal sensor and automatic thermal monitoring facilities. See\r
- Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display\r
- Model 0F_0H.\r
+ Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r
\r
@param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bit 0] Thermal Status (RO):.\r
+ /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 ThermalStatus:1;\r
///\r
- /// [Bit 1] Thermal Status Log (R/W):.\r
+ /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 ThermalStatusLog:1;\r
///\r
- /// [Bit 2] PROCHOT # or FORCEPR# event (RO).\r
+ /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_FORCEPR_Event:1;\r
///\r
- /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).\r
+ /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_FORCEPR_Log:1;\r
///\r
- /// [Bit 4] Critical Temperature Status (RO).\r
+ /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempStatus:1;\r
///\r
/// [Bit 5] Critical Temperature Status log (R/WC0).\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempStatusLog:1;\r
///\r
/// automatically reduce power consumption in response to TCC activation.\r
/// 0 = Disabled. Note: In some products clearing this bit might be\r
/// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r
- /// thermal throttling will still be activated. Introduced at Display\r
- /// Family / Display Model 0F_0H.\r
+ /// thermal throttling will still be activated. The default value of this\r
+ /// field varies with product. See respective tables where default value is\r
+ /// listed. Introduced at Display Family / Display Model 0F_0H.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
+ /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
/// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r
/// Family / Display Model 06_0FH.\r
///\r
UINT32 Reserved6:3;\r
///\r
/// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r
- /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup\r
+ /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r
/// question that allows users to specify when the installed OS does not\r
- /// support CPUID functions greater than 3. Before setting this bit, BIOS\r
+ /// support CPUID functions greater than 2. Before setting this bit, BIOS\r
/// must execute the CPUID.0H and examine the maximum value returned in\r
- /// EAX[7:0]. If the maximum value is greater than 3, the bit is\r
- /// supported. Otherwise, the bit is not supported. Writing to this bit\r
- /// when the maximum value is greater than 3 may generate a #GP exception.\r
+ /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r
+ /// supported. Otherwise, this bit is not supported. Setting this bit when\r
+ /// the maximum value is not greater than 2 may generate a #GP exception.\r
/// Setting this bit may cause unexpected behavior in software that\r
- /// depends on the availability of CPUID leaves greater than 3. Introduced\r
+ /// depends on the availability of CPUID leaves greater than 2. Introduced\r
/// at Display Family / Display Model 0F_03H.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
\r
\r
/**\r
- Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.\r
- If CPUID.0AH: EDX[4:0] > 1.\r
+ Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r
+ CPUID.0AH: EDX[4:0] > 1.\r
\r
@param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.\r
- If CPUID.0AH: EDX[4:0] > 2.\r
+ Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r
+ CPUID.0AH: EDX[4:0] > 2.\r
\r
@param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
UINT32 MemoryType:4;\r
///\r
- /// [Bit 54] If bit 54 is read as 1, the logical processor reports\r
- /// information in the VM-exit instruction-information field on VM exits\r
- /// due to execution of the INS and OUTS instructions. This reporting is\r
- /// done only if this bit is read as 1.\r
+ /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r
+ /// the VM-exit instruction-information field on VM exitsdue to execution\r
+ /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r
+ /// is done only if this bit is read as 1.\r
///\r
UINT32 InsOutsReporting:1;\r
///\r
/// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
///\r
UINT32 WaitForSipiActivityStateSupported:1;\r
- UINT32 Reserved1:6;\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
+ /// in VMX operation. If the processor supports Intel PT but does not allow\r
+ /// it to be used in VMX operation, execution of VMXON clears\r
+ /// IA32_RTIT_CTL.TraceEn (see \93VMXON\97Enter VMX Operation\94 in Chapter 30);\r
+ /// any attempt to set that bit while in VMX operation (including VMX root\r
+ /// operation) using the WRMSR instruction causes a general-protection\r
+ /// exception.\r
+ ///\r
+ UINT32 ProcessorTraceSupported:1;\r
///\r
/// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
/// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
- /// See Section 34.15.6.4.\r
+ /// See Section 34.15.6.3.\r
///\r
UINT32 SmBaseMsrSupported:1;\r
///\r
/// information fields.\r
///\r
UINT32 VmWriteSupported:1;\r
- UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 30] If read as 1, VM entry allows injection of a software\r
+ /// interrupt, software exception, or privileged software exception with an\r
+ /// instruction length of 0.\r
+ ///\r
+ UINT32 VmInjectSupported:1;\r
+ UINT32 Reserved2:1;\r
///\r
/// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
/// processor.\r
///\r
struct {\r
///\r
- /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated\r
+ /// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated\r
/// Code Modules (ACMs)".\r
///\r
UINT32 Lock:1;\r
UINT32 Reserved1:15;\r
///\r
- /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with\r
+ /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with\r
/// Authenticated Code Modules (ACMs)".\r
///\r
UINT32 SGX_SVN_SINIT:8;\r
/**\r
DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
buffer management area, which is used to manage the BTS and PEBS buffers.\r
- See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r
+ See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r
= 1.\r
\r
[Bits 31..0] The linear address of the first byte of the DS buffer\r
\r
\r
/**\r
- Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =\r
- 1 ).\r
+ Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r
+ =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r
\r
@param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r
@param EAX Lower 32-bits of MSR value.\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.\r
\r
**/\r
\r
\r
\r
/**\r
- Unique. Last Branch Record 0 From IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the source instruction for one of the last eight\r
- branches, exceptions, or interrupts taken by the processor. See also: -\r
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,\r
- Interrupt, and Exception Recording (Pentium M Processors).".\r
+ Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction . See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.5.\r
\r
@param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Unique. Last Branch Record 0 To IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction for one of the last eight\r
- branches, exceptions, or interrupts taken by the processor.\r
+ Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. The To_IP part of the\r
+ stack contains pointers to the destination instruction.\r
\r
@param ECX MSR_ATOM_LASTBRANCH_n_TO_IP\r
@param EAX Lower 32-bits of MSR value.\r
UINT32 Reserved1:2;\r
///\r
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 35-2.\r
+ /// Table 35-2. Default value is 0.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See\r
+ /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 35-2.\r
///\r
UINT32 PEBS:1;\r
\r
\r
/**\r
- Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
- Facilities.".\r
-\r
- @param ECX MSR_ATOM_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
- @note MSR_ATOM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
-**/\r
-#define MSR_ATOM_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
-/**\r
- Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling\r
+ Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r
(PEBS).".\r
\r
@param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)\r
} MSR_ATOM_PEBS_ENABLE_REGISTER;\r
\r
\r
-/**\r
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_ATOM_MC3_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_CTL);\r
- AsmWriteMsr64 (MSR_ATOM_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
-**/\r
-#define MSR_ATOM_MC3_CTL 0x0000040C\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_ATOM_MC3_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_ATOM_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
-**/\r
-#define MSR_ATOM_MC3_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC3_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_ATOM_MC3_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_ATOM_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
-**/\r
-#define MSR_ATOM_MC3_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_ATOM_MC4_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_CTL);\r
- AsmWriteMsr64 (MSR_ATOM_MC4_CTL, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
-**/\r
-#define MSR_ATOM_MC4_CTL 0x00000410\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_ATOM_MC4_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_ATOM_MC4_STATUS, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
-**/\r
-#define MSR_ATOM_MC4_STATUS 0x00000411\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC4_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_ATOM_MC4_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_ATOM_MC4_ADDR, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
-**/\r
-#define MSR_ATOM_MC4_ADDR 0x00000412\r
-\r
-\r
/**\r
Package. Package C2 Residency Note: C-state values are processor specific\r
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.13.\r
\r
**/\r
\r
Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
Facilities.".\r
\r
- @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
@param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;\r
+ MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
\r
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
@endcode\r
- @note MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
+ @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
- MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS\r
+ MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
///\r
UINT32 Ovf_FixedCtr2:1;\r
UINT32 Reserved2:20;\r
///\r
- /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical\r
+ /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
/// Addresses (ToPA).".\r
///\r
UINT32 Trace_ToPA_PMI:1;\r
/// All bit fields as a 64-bit value\r
///\r
UINT64 Uint64;\r
-} MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;\r
+} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
\r
/**\r
UINT64 Uint64;\r
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r
+\r
#endif\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.2.\r
\r
**/\r
\r
\r
/**\r
Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the source instruction for one of the last four\r
- branches, exceptions, or interrupts taken by the processor. See also: -\r
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,\r
- Interrupt, and Exception Recording (Pentium M Processors).".\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction. See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.5.\r
\r
@param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP\r
@param EAX Lower 32-bits of MSR value.\r
\r
/**\r
Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction for one of the last four\r
- branches, exceptions, or interrupts taken by the processor.\r
+ record registers on the last branch record stack. This To_IP part of the\r
+ stack contains pointers to the destination instruction.\r
\r
@param ECX MSR_CORE2_LASTBRANCH_n_TO_IP\r
@param EAX Lower 32-bits of MSR value.\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See\r
+ /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 35-2.\r
///\r
UINT32 PEBS:1;\r
#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r
\r
\r
-/**\r
- Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
- Facilities.".\r
-\r
- @param ECX MSR_CORE2_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
-**/\r
-#define MSR_CORE2_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
/**\r
Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r
\r
- @param ECX MSR_CORE2_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);\r
@endcode\r
- @note MSR_CORE2_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.\r
+ @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_CORE2_PERF_GLOBAL_STAUS 0x0000038E\r
+#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r
\r
\r
/**\r
\r
\r
/**\r
- Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling\r
+ Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r
(PEBS).".\r
\r
@param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)\r
} MSR_CORE2_PEBS_ENABLE_REGISTER;\r
\r
\r
-/**\r
- Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_CORE2_MC4_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
-**/\r
-#define MSR_CORE2_MC4_CTL 0x0000040C\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_CORE2_MC4_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_MC4_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC4_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_CORE2_MC4_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
-**/\r
-#define MSR_CORE2_MC4_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_CORE2_MC3_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
-**/\r
-#define MSR_CORE2_MC3_CTL 0x00000410\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_CORE2_MC3_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_MC3_STATUS 0x00000411\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC3_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_CORE2_MC3_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
-**/\r
-#define MSR_CORE2_MC3_ADDR 0x00000412\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC3_MISC (0x00000413)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r
-**/\r
-#define MSR_CORE2_MC3_MISC 0x00000413\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_CTL (0x00000414)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
-**/\r
-#define MSR_CORE2_MC5_CTL 0x00000414\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_STATUS (0x00000415)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_MC5_STATUS 0x00000415\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_ADDR (0x00000416)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
-**/\r
-#define MSR_CORE2_MC5_ADDR 0x00000416\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_MISC (0x00000417)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
-**/\r
-#define MSR_CORE2_MC5_MISC 0x00000417\r
-\r
-\r
-/**\r
- Unique. Apply to Intel Xeon processor 7400 series (processor signature\r
- 06_1D) only. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS." and Chapter 23.\r
-\r
- @param ECX MSR_CORE2_MC6_STATUS (0x00000419)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_MC6_STATUS 0x00000419\r
-\r
-\r
/**\r
Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon\r
processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.19.\r
\r
**/\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
- Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.\r
+ Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.\r
\r
@param ECX MSR_CORE_P5_MC_ADDR (0x00000000)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.\r
+ Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.\r
\r
@param ECX MSR_CORE_P5_MC_TYPE (0x00000001)\r
@param EAX Lower 32-bits of MSR value.\r
Unique. Last Branch Record n (R/W) One of 8 last branch record registers on\r
the last branch record stack: bits 31-0 hold the 'from' address and bits\r
63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at\r
- 1C9H - Section 17.12, "Last Branch, Interrupt, and Exception Recording\r
+ 1C9H - Section 17.13, "Last Branch, Interrupt, and Exception Recording\r
(Pentium M Processors).".\r
\r
@param ECX MSR_CORE_LASTBRANCH_n\r
/// thermal sensor indicates that the die temperature is at the\r
/// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r
/// TM2 will reduce the bus to core ratio and voltage according to the\r
- /// value last written to MSR_THERM2_CTL bits 15:0.\r
- /// When this bit is clear (0, default), the processor does not change\r
- /// the VID signals or the bus to core ratio when the processor enters a\r
- /// thermal managed state. If the TM2 feature flag (ECX[8]) is not set\r
- /// to 1 after executing CPUID with EAX = 1, then this feature is not\r
- /// supported and BIOS must not alter the contents of this bit location.\r
- /// The processor is operating out of spec if both this bit and the TM1\r
- /// bit are set to disabled states.\r
+ /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear\r
+ /// (0, default), the processor does not change the VID signals or the bus\r
+ /// to core ratio when the processor enters a thermal managed state. If\r
+ /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID\r
+ /// with EAX = 1, then this feature is not supported and BIOS must not\r
+ /// alter the contents of this bit location. The processor is operating\r
+ /// out of spec if both this bit and the TM1 bit are set to disabled\r
+ /// states.\r
///\r
UINT32 TM2:1;\r
UINT32 Reserved5:2;\r
///\r
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this\r
/// bit may cause behavior in software that depends on the availability of\r
- /// CPUID leaves greater than 3.\r
+ /// CPUID leaves greater than 2.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
UINT32 Reserved9:9;\r
#define MSR_CORE_MC4_ADDR 0x0000040E\r
\r
\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_CORE_MC3_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC3_CTL);\r
- AsmWriteMsr64 (MSR_CORE_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
-**/\r
-#define MSR_CORE_MC3_CTL 0x00000410\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_CORE_MC3_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_CORE_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
-**/\r
-#define MSR_CORE_MC3_STATUS 0x00000411\r
-\r
-\r
/**\r
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
register is either not implemented or contains no address if the ADDRV flag\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.12.\r
\r
**/\r
\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
+/**\r
+ Package. Configured State of Enabled Processor Core Count and Logical\r
+ Processor Count (RO) - After a Power-On RESET, enumerates factory\r
+ configuration of the number of processor cores and logical processors in the\r
+ physical package. - Following the sequence of (i) BIOS modified a\r
+ Configuration Mask which selects a subset of processor cores to be active\r
+ post RESET and (ii) a RESET event after the modification, enumerates the\r
+ current configuration of enabled processor core count and logical processor\r
+ count in the physical package.\r
+\r
+ @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);\r
+ @endcode\r
+ @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.\r
+**/\r
+#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are\r
+ /// currently enabled (by either factory configuration or BIOS\r
+ /// configuration) in the physical package.\r
+ ///\r
+ UINT32 Core_Count:16;\r
+ ///\r
+ /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that\r
+ /// are currently enabled (by either factory configuration or BIOS\r
+ /// configuration) in the physical package.\r
+ ///\r
+ UINT32 Thread_Count:16;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. A Hardware Assigned ID for the Logical Processor (RO).\r
+\r
+ @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);\r
+ @endcode\r
+ @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.\r
+**/\r
+#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific\r
+ /// numerical. value physically assigned to each logical processor. This\r
+ /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within\r
+ /// a physical package.\r
+ ///\r
+ UINT32 Logical_Processor_ID:8;\r
+ UINT32 Reserved1:24;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;\r
+\r
+\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r
\r
\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- * Bank MC5 reports MC error from the Intel QPI 0 module.\r
- * Bank MC6 reports MC error from the integrated I/O module.\r
- * Bank MC7 reports MC error from the home agent HA 0.\r
- * Bank MC8 reports MC error from the home agent HA 1.\r
- * Banks MC9 through MC16 report MC error from each channel of the integrated\r
- memory controllers.\r
- * Bank MC17 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.\r
- * Bank MC18 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.\r
- * Bank MC19 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.\r
- * Bank MC20 reports MC error from the Intel QPI 1 module.\r
- * Bank MC21 reports MC error from the Intel QPI 2 module.\r
-\r
- @param ECX MSR_HASWELL_E_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
- MSR_HASWELL_E_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
- MSR_HASWELL_E_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
- MSR_HASWELL_E_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
- MSR_HASWELL_E_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
- MSR_HASWELL_E_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
- MSR_HASWELL_E_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
- MSR_HASWELL_E_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
- MSR_HASWELL_E_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
- MSR_HASWELL_E_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
- MSR_HASWELL_E_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
- MSR_HASWELL_E_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
- MSR_HASWELL_E_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
- MSR_HASWELL_E_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
- MSR_HASWELL_E_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
- MSR_HASWELL_E_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
- MSR_HASWELL_E_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_E_MC5_CTL 0x00000414\r
-#define MSR_HASWELL_E_MC6_CTL 0x00000418\r
-#define MSR_HASWELL_E_MC7_CTL 0x0000041C\r
-#define MSR_HASWELL_E_MC8_CTL 0x00000420\r
-#define MSR_HASWELL_E_MC9_CTL 0x00000424\r
-#define MSR_HASWELL_E_MC10_CTL 0x00000428\r
-#define MSR_HASWELL_E_MC11_CTL 0x0000042C\r
-#define MSR_HASWELL_E_MC12_CTL 0x00000430\r
-#define MSR_HASWELL_E_MC13_CTL 0x00000434\r
-#define MSR_HASWELL_E_MC14_CTL 0x00000438\r
-#define MSR_HASWELL_E_MC15_CTL 0x0000043C\r
-#define MSR_HASWELL_E_MC16_CTL 0x00000440\r
-#define MSR_HASWELL_E_MC17_CTL 0x00000444\r
-#define MSR_HASWELL_E_MC18_CTL 0x00000448\r
-#define MSR_HASWELL_E_MC19_CTL 0x0000044C\r
-#define MSR_HASWELL_E_MC20_CTL 0x00000450\r
-#define MSR_HASWELL_E_MC21_CTL 0x00000454\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_HASWELL_E_MCi_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
- MSR_HASWELL_E_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
- MSR_HASWELL_E_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
- MSR_HASWELL_E_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
- MSR_HASWELL_E_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
- MSR_HASWELL_E_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
- MSR_HASWELL_E_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
- MSR_HASWELL_E_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
- MSR_HASWELL_E_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
- MSR_HASWELL_E_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
- MSR_HASWELL_E_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
- MSR_HASWELL_E_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
- MSR_HASWELL_E_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
- MSR_HASWELL_E_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
- MSR_HASWELL_E_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
- MSR_HASWELL_E_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
- MSR_HASWELL_E_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_E_MC5_STATUS 0x00000415\r
-#define MSR_HASWELL_E_MC6_STATUS 0x00000419\r
-#define MSR_HASWELL_E_MC7_STATUS 0x0000041D\r
-#define MSR_HASWELL_E_MC8_STATUS 0x00000421\r
-#define MSR_HASWELL_E_MC9_STATUS 0x00000425\r
-#define MSR_HASWELL_E_MC10_STATUS 0x00000429\r
-#define MSR_HASWELL_E_MC11_STATUS 0x0000042D\r
-#define MSR_HASWELL_E_MC12_STATUS 0x00000431\r
-#define MSR_HASWELL_E_MC13_STATUS 0x00000435\r
-#define MSR_HASWELL_E_MC14_STATUS 0x00000439\r
-#define MSR_HASWELL_E_MC15_STATUS 0x0000043D\r
-#define MSR_HASWELL_E_MC16_STATUS 0x00000441\r
-#define MSR_HASWELL_E_MC17_STATUS 0x00000445\r
-#define MSR_HASWELL_E_MC18_STATUS 0x00000449\r
-#define MSR_HASWELL_E_MC19_STATUS 0x0000044D\r
-#define MSR_HASWELL_E_MC20_STATUS 0x00000451\r
-#define MSR_HASWELL_E_MC21_STATUS 0x00000455\r
-/// @}\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_HASWELL_E_MCi_ADDR\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_ADDR, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
- MSR_HASWELL_E_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
- MSR_HASWELL_E_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
- MSR_HASWELL_E_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
- MSR_HASWELL_E_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
- MSR_HASWELL_E_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
- MSR_HASWELL_E_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
- MSR_HASWELL_E_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
- MSR_HASWELL_E_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
- MSR_HASWELL_E_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
- MSR_HASWELL_E_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
- MSR_HASWELL_E_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
- MSR_HASWELL_E_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
- MSR_HASWELL_E_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
- MSR_HASWELL_E_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
- MSR_HASWELL_E_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
- MSR_HASWELL_E_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_E_MC5_ADDR 0x00000416\r
-#define MSR_HASWELL_E_MC6_ADDR 0x0000041A\r
-#define MSR_HASWELL_E_MC7_ADDR 0x0000041E\r
-#define MSR_HASWELL_E_MC8_ADDR 0x00000422\r
-#define MSR_HASWELL_E_MC9_ADDR 0x00000426\r
-#define MSR_HASWELL_E_MC10_ADDR 0x0000042A\r
-#define MSR_HASWELL_E_MC11_ADDR 0x0000042E\r
-#define MSR_HASWELL_E_MC12_ADDR 0x00000432\r
-#define MSR_HASWELL_E_MC13_ADDR 0x00000436\r
-#define MSR_HASWELL_E_MC14_ADDR 0x0000043A\r
-#define MSR_HASWELL_E_MC15_ADDR 0x0000043E\r
-#define MSR_HASWELL_E_MC16_ADDR 0x00000442\r
-#define MSR_HASWELL_E_MC17_ADDR 0x00000446\r
-#define MSR_HASWELL_E_MC18_ADDR 0x0000044A\r
-#define MSR_HASWELL_E_MC19_ADDR 0x0000044E\r
-#define MSR_HASWELL_E_MC20_ADDR 0x00000452\r
-#define MSR_HASWELL_E_MC21_ADDR 0x00000456\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_HASWELL_E_MCi_MISC\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_MISC);\r
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_MISC, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
- MSR_HASWELL_E_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
- MSR_HASWELL_E_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
- MSR_HASWELL_E_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
- MSR_HASWELL_E_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
- MSR_HASWELL_E_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
- MSR_HASWELL_E_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
- MSR_HASWELL_E_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
- MSR_HASWELL_E_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
- MSR_HASWELL_E_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
- MSR_HASWELL_E_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
- MSR_HASWELL_E_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
- MSR_HASWELL_E_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
- MSR_HASWELL_E_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
- MSR_HASWELL_E_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
- MSR_HASWELL_E_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
- MSR_HASWELL_E_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_E_MC5_MISC 0x00000417\r
-#define MSR_HASWELL_E_MC6_MISC 0x0000041B\r
-#define MSR_HASWELL_E_MC7_MISC 0x0000041F\r
-#define MSR_HASWELL_E_MC8_MISC 0x00000423\r
-#define MSR_HASWELL_E_MC9_MISC 0x00000427\r
-#define MSR_HASWELL_E_MC10_MISC 0x0000042B\r
-#define MSR_HASWELL_E_MC11_MISC 0x0000042F\r
-#define MSR_HASWELL_E_MC12_MISC 0x00000433\r
-#define MSR_HASWELL_E_MC13_MISC 0x00000437\r
-#define MSR_HASWELL_E_MC14_MISC 0x0000043B\r
-#define MSR_HASWELL_E_MC15_MISC 0x0000043F\r
-#define MSR_HASWELL_E_MC16_MISC 0x00000443\r
-#define MSR_HASWELL_E_MC17_MISC 0x00000447\r
-#define MSR_HASWELL_E_MC18_MISC 0x0000044B\r
-#define MSR_HASWELL_E_MC19_MISC 0x0000044F\r
-#define MSR_HASWELL_E_MC20_MISC 0x00000453\r
-#define MSR_HASWELL_E_MC21_MISC 0x00000457\r
-/// @}\r
-\r
-\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
\r
\r
\r
/**\r
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+ Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.\r
\r
@param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)\r
@param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r
@endcode\r
@note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r
\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
+ /// to enable DRAM RAPL mode 0 (Direct VR).\r
+ ///\r
+ UINT32 Energy:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;\r
+\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r
\r
\r
+/**\r
+ Package. Configuration of PCIE PLL Relative to BCLK(R/W).\r
+\r
+ @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz\r
+ /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use\r
+ /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz\r
+ /// operation.\r
+ ///\r
+ UINT32 PCIERatio:2;\r
+ ///\r
+ /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of\r
+ /// PCIE Ratio.\r
+ ///\r
+ UINT32 LPLLSelect:1;\r
+ ///\r
+ /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out\r
+ /// before re-locking Gen2/Gen3 PLLs.\r
+ ///\r
+ UINT32 LONGRESET:1;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Reserved (R/O) Reads return 0.\r
+\r
+ @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
refers to processor core frequency).\r
\r
/**\r
THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r
- ECX=0):EBX.PQM[bit 12] = 1.\r
+ ECX=0):EBX.RDT-M[bit 12] = 1.\r
\r
@param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)\r
@param EAX Lower 32-bits of MSR value.\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.11.\r
\r
**/\r
\r
UINT32 InterruptResponseTimeLimit:10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
- /// unit of the interrupt response time limit. The following time unit\r
- /// encodings are supported:\r
- ///\r
- /// 000b: 1 ns\r
- /// 001b: 32 ns\r
- /// 010b: 1024 ns\r
- /// 011b: 32768 ns\r
- /// 100b: 1048576 ns\r
- /// 101b: 33554432 ns.\r
+ /// unit of the interrupt response time limit. See Table 35-18 for\r
+ /// supported time unit encodings.\r
///\r
UINT32 TimeUnit:3;\r
UINT32 Reserved1:2;\r
UINT32 InterruptResponseTimeLimit:10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
- /// unit of the interrupt response time limit. The following time unit\r
- /// encodings are supported:\r
- ///\r
- /// 000b: 1 ns\r
- /// 001b: 32 ns\r
- /// 010b: 1024 ns\r
- /// 011b: 32768 ns\r
- /// 100b: 1048576 ns\r
- /// 101b: 33554432 ns.\r
+ /// unit of the interrupt response time limit. See Table 35-18 for\r
+ /// supported time unit encodings.\r
///\r
UINT32 TimeUnit:3;\r
UINT32 Reserved1:2;\r
} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;\r
\r
\r
-/**\r
- Package. Silicon Debug Feature Control (R/W) See Table 35-2.\r
-\r
- @param ECX MSR_HASWELL_IA32_DEBUG_FEATURE (0x00000C80)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE);\r
- AsmWriteMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE, Msr);\r
- @endcode\r
- @note MSR_HASWELL_IA32_DEBUG_FEATURE is defined as IA32_DEBUG_FEATURE in SDM.\r
-**/\r
-#define MSR_HASWELL_IA32_DEBUG_FEATURE 0x00000C80\r
-\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;\r
\r
\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
/**\r
Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
RAPL Domains.".\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.10.\r
\r
**/\r
\r
} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
/**\r
Package. Base TDP Ratio (R/O).\r
\r
\r
\r
/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.". Bank MC5 reports MC error from the Intel\r
- QPI module.\r
-\r
- * Bank MC6 reports MC error from the integrated I/O module.\r
- * Banks MC7 and MC 8 report MC error from the two home agents.\r
- * Banks MC9 through MC 16 report MC error from each channel of the integrated\r
- memory controllers.\r
- * Banks MC17 through MC31 reports MC error from a specific CBo\r
- (core broadcast) and its corresponding slice of L3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC22_CTL is defined as MSR_MC22_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC23_CTL is defined as MSR_MC23_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC24_CTL is defined as MSR_MC24_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC25_CTL is defined as MSR_MC25_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC26_CTL is defined as MSR_MC26_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC27_CTL is defined as MSR_MC27_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC28_CTL is defined as MSR_MC28_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC29_CTL is defined as MSR_MC29_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC30_CTL is defined as MSR_MC30_CTL in SDM.\r
- MSR_IVY_BRIDGE_MC31_CTL is defined as MSR_MC31_CTL in SDM.\r
- @{\r
+ Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_MC5_CTL 0x00000414\r
-#define MSR_IVY_BRIDGE_MC6_CTL 0x00000418\r
-#define MSR_IVY_BRIDGE_MC7_CTL 0x0000041C\r
-#define MSR_IVY_BRIDGE_MC8_CTL 0x00000420\r
-#define MSR_IVY_BRIDGE_MC9_CTL 0x00000424\r
-#define MSR_IVY_BRIDGE_MC10_CTL 0x00000428\r
-#define MSR_IVY_BRIDGE_MC11_CTL 0x0000042C\r
-#define MSR_IVY_BRIDGE_MC12_CTL 0x00000430\r
-#define MSR_IVY_BRIDGE_MC13_CTL 0x00000434\r
-#define MSR_IVY_BRIDGE_MC14_CTL 0x00000438\r
-#define MSR_IVY_BRIDGE_MC15_CTL 0x0000043C\r
-#define MSR_IVY_BRIDGE_MC16_CTL 0x00000440\r
-#define MSR_IVY_BRIDGE_MC17_CTL 0x00000444\r
-#define MSR_IVY_BRIDGE_MC18_CTL 0x00000448\r
-#define MSR_IVY_BRIDGE_MC19_CTL 0x0000044C\r
-#define MSR_IVY_BRIDGE_MC20_CTL 0x00000450\r
-#define MSR_IVY_BRIDGE_MC21_CTL 0x00000454\r
-#define MSR_IVY_BRIDGE_MC22_CTL 0x00000458\r
-#define MSR_IVY_BRIDGE_MC23_CTL 0x0000045C\r
-#define MSR_IVY_BRIDGE_MC24_CTL 0x00000460\r
-#define MSR_IVY_BRIDGE_MC25_CTL 0x00000464\r
-#define MSR_IVY_BRIDGE_MC26_CTL 0x00000468\r
-#define MSR_IVY_BRIDGE_MC27_CTL 0x0000046C\r
-#define MSR_IVY_BRIDGE_MC28_CTL 0x00000470\r
-#define MSR_IVY_BRIDGE_MC29_CTL 0x00000474\r
-#define MSR_IVY_BRIDGE_MC30_CTL 0x00000478\r
-#define MSR_IVY_BRIDGE_MC31_CTL 0x0000047C\r
-/// @}\r
+#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 5:0] Recoverable Address LSB.\r
+ ///\r
+ UINT32 RecoverableAddressLSB:6;\r
+ ///\r
+ /// [Bits 8:6] Address Mode.\r
+ ///\r
+ UINT32 AddressMode:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bits 31:16] PCI Express Requestor ID.\r
+ ///\r
+ UINT32 PCIExpressRequestorID:16;\r
+ ///\r
+ /// [Bits 39:32] PCI Express Segment Number.\r
+ ///\r
+ UINT32 PCIExpressSegmentNumber:8;\r
+ UINT32 Reserved2:24;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r
\r
\r
/**\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
\r
- Bank MC20 reports MC error from a specific CBo (core broadcast) and\r
- its corresponding slice of L3.\r
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
+ and its corresponding slice of L3.\r
\r
- @param ECX MSR_IVY_BRIDGE_MCi_STATUS\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_STATUS, Msr);\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);\r
@endcode\r
- @note MSR_IVY_BRIDGE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC22_STATUS is defined as MSR_MC22_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC23_STATUS is defined as MSR_MC23_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC24_STATUS is defined as MSR_MC24_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC25_STATUS is defined as MSR_MC25_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC26_STATUS is defined as MSR_MC26_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC27_STATUS is defined as MSR_MC27_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC28_STATUS is defined as MSR_MC28_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC29_STATUS is defined as MSR_MC29_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC30_STATUS is defined as MSR_MC30_STATUS in SDM.\r
- MSR_IVY_BRIDGE_MC31_STATUS is defined as MSR_MC31_STATUS in SDM.\r
+ @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_MC5_STATUS 0x00000415\r
-#define MSR_IVY_BRIDGE_MC6_STATUS 0x00000419\r
-#define MSR_IVY_BRIDGE_MC7_STATUS 0x0000041D\r
-#define MSR_IVY_BRIDGE_MC8_STATUS 0x00000421\r
-#define MSR_IVY_BRIDGE_MC9_STATUS 0x00000425\r
-#define MSR_IVY_BRIDGE_MC10_STATUS 0x00000429\r
-#define MSR_IVY_BRIDGE_MC11_STATUS 0x0000042D\r
-#define MSR_IVY_BRIDGE_MC12_STATUS 0x00000431\r
-#define MSR_IVY_BRIDGE_MC13_STATUS 0x00000435\r
-#define MSR_IVY_BRIDGE_MC14_STATUS 0x00000439\r
-#define MSR_IVY_BRIDGE_MC15_STATUS 0x0000043D\r
-#define MSR_IVY_BRIDGE_MC16_STATUS 0x00000441\r
-#define MSR_IVY_BRIDGE_MC17_STATUS 0x00000445\r
-#define MSR_IVY_BRIDGE_MC18_STATUS 0x00000449\r
-#define MSR_IVY_BRIDGE_MC19_STATUS 0x0000044D\r
-#define MSR_IVY_BRIDGE_MC20_STATUS 0x00000451\r
-#define MSR_IVY_BRIDGE_MC21_STATUS 0x00000455\r
-#define MSR_IVY_BRIDGE_MC22_STATUS 0x00000459\r
-#define MSR_IVY_BRIDGE_MC23_STATUS 0x0000045D\r
-#define MSR_IVY_BRIDGE_MC24_STATUS 0x00000461\r
-#define MSR_IVY_BRIDGE_MC25_STATUS 0x00000465\r
-#define MSR_IVY_BRIDGE_MC26_STATUS 0x00000469\r
-#define MSR_IVY_BRIDGE_MC27_STATUS 0x0000046D\r
-#define MSR_IVY_BRIDGE_MC28_STATUS 0x00000471\r
-#define MSR_IVY_BRIDGE_MC29_STATUS 0x00000475\r
-#define MSR_IVY_BRIDGE_MC30_STATUS 0x00000479\r
-#define MSR_IVY_BRIDGE_MC31_STATUS 0x0000047D\r
+#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474\r
+#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478\r
+#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C\r
/// @}\r
\r
\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
\r
- @param ECX MSR_IVY_BRIDGE_MCi_ADDR\r
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
+ and its corresponding slice of L3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_ADDR, Msr);\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);\r
@endcode\r
- @note MSR_IVY_BRIDGE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC22_ADDR is defined as MSR_MC22_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC23_ADDR is defined as MSR_MC23_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC24_ADDR is defined as MSR_MC24_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC25_ADDR is defined as MSR_MC25_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC26_ADDR is defined as MSR_MC26_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC27_ADDR is defined as MSR_MC27_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC28_ADDR is defined as MSR_MC28_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC29_ADDR is defined as MSR_MC29_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC30_ADDR is defined as MSR_MC30_ADDR in SDM.\r
- MSR_IVY_BRIDGE_MC31_ADDR is defined as MSR_MC31_ADDR in SDM.\r
+ @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_MC5_ADDR 0x00000416\r
-#define MSR_IVY_BRIDGE_MC6_ADDR 0x0000041A\r
-#define MSR_IVY_BRIDGE_MC7_ADDR 0x0000041E\r
-#define MSR_IVY_BRIDGE_MC8_ADDR 0x00000422\r
-#define MSR_IVY_BRIDGE_MC9_ADDR 0x00000426\r
-#define MSR_IVY_BRIDGE_MC10_ADDR 0x0000042A\r
-#define MSR_IVY_BRIDGE_MC11_ADDR 0x0000042E\r
-#define MSR_IVY_BRIDGE_MC12_ADDR 0x00000432\r
-#define MSR_IVY_BRIDGE_MC13_ADDR 0x00000436\r
-#define MSR_IVY_BRIDGE_MC14_ADDR 0x0000043A\r
-#define MSR_IVY_BRIDGE_MC15_ADDR 0x0000043E\r
-#define MSR_IVY_BRIDGE_MC16_ADDR 0x00000442\r
-#define MSR_IVY_BRIDGE_MC17_ADDR 0x00000446\r
-#define MSR_IVY_BRIDGE_MC18_ADDR 0x0000044A\r
-#define MSR_IVY_BRIDGE_MC19_ADDR 0x0000044E\r
-#define MSR_IVY_BRIDGE_MC20_ADDR 0x00000452\r
-#define MSR_IVY_BRIDGE_MC21_ADDR 0x00000456\r
-#define MSR_IVY_BRIDGE_MC22_ADDR 0x0000045A\r
-#define MSR_IVY_BRIDGE_MC23_ADDR 0x0000045E\r
-#define MSR_IVY_BRIDGE_MC24_ADDR 0x00000462\r
-#define MSR_IVY_BRIDGE_MC25_ADDR 0x00000466\r
-#define MSR_IVY_BRIDGE_MC26_ADDR 0x0000046A\r
-#define MSR_IVY_BRIDGE_MC27_ADDR 0x0000046E\r
-#define MSR_IVY_BRIDGE_MC28_ADDR 0x00000472\r
-#define MSR_IVY_BRIDGE_MC29_ADDR 0x00000476\r
-#define MSR_IVY_BRIDGE_MC30_ADDR 0x0000047A\r
-#define MSR_IVY_BRIDGE_MC31_ADDR 0x0000047E\r
+#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475\r
+#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479\r
+#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D\r
/// @}\r
\r
\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
\r
- @param ECX MSR_IVY_BRIDGE_MCi_MISC\r
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
+ and its corresponding slice of L3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_MISC);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_MISC, Msr);\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);\r
@endcode\r
- @note MSR_IVY_BRIDGE_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC22_MISC is defined as MSR_MC22_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC23_MISC is defined as MSR_MC23_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC24_MISC is defined as MSR_MC24_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC25_MISC is defined as MSR_MC25_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC26_MISC is defined as MSR_MC26_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC27_MISC is defined as MSR_MC27_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC28_MISC is defined as MSR_MC28_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC29_MISC is defined as MSR_MC29_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC30_MISC is defined as MSR_MC30_MISC in SDM.\r
- MSR_IVY_BRIDGE_MC31_MISC is defined as MSR_MC31_MISC in SDM.\r
+ @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_MC5_MISC 0x00000417\r
-#define MSR_IVY_BRIDGE_MC6_MISC 0x0000041B\r
-#define MSR_IVY_BRIDGE_MC7_MISC 0x0000041F\r
-#define MSR_IVY_BRIDGE_MC8_MISC 0x00000423\r
-#define MSR_IVY_BRIDGE_MC9_MISC 0x00000427\r
-#define MSR_IVY_BRIDGE_MC10_MISC 0x0000042B\r
-#define MSR_IVY_BRIDGE_MC11_MISC 0x0000042F\r
-#define MSR_IVY_BRIDGE_MC12_MISC 0x00000433\r
-#define MSR_IVY_BRIDGE_MC13_MISC 0x00000437\r
-#define MSR_IVY_BRIDGE_MC14_MISC 0x0000043B\r
-#define MSR_IVY_BRIDGE_MC15_MISC 0x0000043F\r
-#define MSR_IVY_BRIDGE_MC16_MISC 0x00000443\r
-#define MSR_IVY_BRIDGE_MC17_MISC 0x00000447\r
-#define MSR_IVY_BRIDGE_MC18_MISC 0x0000044B\r
-#define MSR_IVY_BRIDGE_MC19_MISC 0x0000044F\r
-#define MSR_IVY_BRIDGE_MC20_MISC 0x00000453\r
-#define MSR_IVY_BRIDGE_MC21_MISC 0x00000457\r
-#define MSR_IVY_BRIDGE_MC22_MISC 0x0000045B\r
-#define MSR_IVY_BRIDGE_MC23_MISC 0x0000045F\r
-#define MSR_IVY_BRIDGE_MC24_MISC 0x00000463\r
-#define MSR_IVY_BRIDGE_MC25_MISC 0x00000467\r
-#define MSR_IVY_BRIDGE_MC26_MISC 0x0000046B\r
-#define MSR_IVY_BRIDGE_MC27_MISC 0x0000046F\r
-#define MSR_IVY_BRIDGE_MC28_MISC 0x00000473\r
-#define MSR_IVY_BRIDGE_MC29_MISC 0x00000477\r
-#define MSR_IVY_BRIDGE_MC30_MISC 0x0000047B\r
-#define MSR_IVY_BRIDGE_MC31_MISC 0x0000047F\r
+#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476\r
+#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A\r
+#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E\r
/// @}\r
\r
\r
/**\r
- Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
\r
- @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)\r
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
+ and its corresponding slice of L3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC\r
@param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;\r
+ UINT64 Msr;\r
\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);\r
@endcode\r
- @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r
+ @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.\r
+ @{\r
**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 5:0] Recoverable Address LSB.\r
- ///\r
- UINT32 RecoverableAddressLSB:6;\r
- ///\r
- /// [Bits 8:6] Address Mode.\r
- ///\r
- UINT32 AddressMode:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bits 31:16] PCI Express Requestor ID.\r
- ///\r
- UINT32 PCIExpressRequestorID:16;\r
- ///\r
- /// [Bits 39:32] PCI Express Segment Number.\r
- ///\r
- UINT32 PCIExpressSegmentNumber:8;\r
- UINT32 Reserved2:24;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r
+#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477\r
+#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B\r
+#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F\r
+/// @}\r
\r
\r
/**\r
\r
\r
/**\r
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".\r
+ Thread. See Section 18.8.1.1, "Precise Event Based Sampling (PEBS).".\r
\r
@param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.6.\r
\r
**/\r
\r
/// auto-demote information.\r
///\r
UINT32 C1AutoDemotion:1;\r
- UINT32 Reserved4:5;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Package C State Demotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateDemotion:1;\r
+ ///\r
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateUndemotion:1;\r
+ UINT32 Reserved4:1;\r
UINT32 Reserved5:32;\r
} Bits;\r
///\r
UINT32 Reserved1:2;\r
///\r
/// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 35-2.\r
+ /// Table 35-2. Default value is 1.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See\r
+ /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 35-2.\r
///\r
UINT32 PEBS:1;\r
\r
/**\r
Core. Last Branch Record Filtering Select Register (R/W) See Section\r
- 17.6.2, "Filtering of Last Branch Records.".\r
+ 17.7.2, "Filtering of Last Branch Records.".\r
\r
@param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)\r
@param EAX Lower 32-bits of MSR value.\r
} MSR_NEHALEM_POWER_CTL_REGISTER;\r
\r
\r
-/**\r
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
- Facilities.".\r
-\r
- @param ECX MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
/**\r
Thread. (RO).\r
\r
- @param ECX MSR_NEHALEM_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)\r
@param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER Msr;\r
+ MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;\r
\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STAUS);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);\r
@endcode\r
- @note MSR_NEHALEM_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.\r
+ @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_PERF_GLOBAL_STAUS 0x0000038E\r
+#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STAUS\r
+ MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
///\r
/// All bit fields as a 64-bit value\r
///\r
UINT64 Uint64;\r
-} MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER;\r
+} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;\r
\r
\r
/**\r
\r
\r
/**\r
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".\r
+ Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".\r
\r
@param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Thread. See Section 18.7.1.2, "Load Latency Performance Monitoring\r
+ Thread. See Section 18.8.1.2, "Load Latency Performance Monitoring\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)\r
#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD\r
\r
\r
-/**\r
- See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_NEHALEM_MCi_MISC\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC0_MISC);\r
- AsmWriteMsr64 (MSR_NEHALEM_MC0_MISC, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_MC0_MISC is defined as MSR_MC0_MISC in SDM.\r
- MSR_NEHALEM_MC1_MISC is defined as MSR_MC1_MISC in SDM.\r
- MSR_NEHALEM_MC2_MISC is defined as MSR_MC2_MISC in SDM.\r
- MSR_NEHALEM_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r
- MSR_NEHALEM_MC4_MISC is defined as MSR_MC4_MISC in SDM.\r
- MSR_NEHALEM_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
- MSR_NEHALEM_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
- MSR_NEHALEM_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
- MSR_NEHALEM_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
- MSR_NEHALEM_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
- MSR_NEHALEM_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
- MSR_NEHALEM_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
- MSR_NEHALEM_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
- MSR_NEHALEM_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
- MSR_NEHALEM_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
- MSR_NEHALEM_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
- MSR_NEHALEM_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
- MSR_NEHALEM_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
- MSR_NEHALEM_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
- MSR_NEHALEM_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
- MSR_NEHALEM_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
- MSR_NEHALEM_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_MC0_MISC 0x00000403\r
-#define MSR_NEHALEM_MC1_MISC 0x00000407\r
-#define MSR_NEHALEM_MC2_MISC 0x0000040B\r
-#define MSR_NEHALEM_MC3_MISC 0x0000040F\r
-#define MSR_NEHALEM_MC4_MISC 0x00000413\r
-#define MSR_NEHALEM_MC5_MISC 0x00000417\r
-#define MSR_NEHALEM_MC6_MISC 0x0000041B\r
-#define MSR_NEHALEM_MC7_MISC 0x0000041F\r
-#define MSR_NEHALEM_MC8_MISC 0x00000423\r
-#define MSR_NEHALEM_MC9_MISC 0x00000427\r
-#define MSR_NEHALEM_MC10_MISC 0x0000042B\r
-#define MSR_NEHALEM_MC11_MISC 0x0000042F\r
-#define MSR_NEHALEM_MC12_MISC 0x00000433\r
-#define MSR_NEHALEM_MC13_MISC 0x00000437\r
-#define MSR_NEHALEM_MC14_MISC 0x0000043B\r
-#define MSR_NEHALEM_MC15_MISC 0x0000043F\r
-#define MSR_NEHALEM_MC16_MISC 0x00000443\r
-#define MSR_NEHALEM_MC17_MISC 0x00000447\r
-#define MSR_NEHALEM_MC18_MISC 0x0000044B\r
-#define MSR_NEHALEM_MC19_MISC 0x0000044F\r
-#define MSR_NEHALEM_MC20_MISC 0x00000453\r
-#define MSR_NEHALEM_MC21_MISC 0x00000457\r
-/// @}\r
-\r
-\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_NEHALEM_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_CTL);\r
- AsmWriteMsr64 (MSR_NEHALEM_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
- MSR_NEHALEM_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
- MSR_NEHALEM_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
- MSR_NEHALEM_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
- MSR_NEHALEM_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
- MSR_NEHALEM_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
- MSR_NEHALEM_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
- MSR_NEHALEM_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
- MSR_NEHALEM_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
- MSR_NEHALEM_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
- MSR_NEHALEM_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
- MSR_NEHALEM_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
- MSR_NEHALEM_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
- MSR_NEHALEM_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
- MSR_NEHALEM_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
- MSR_NEHALEM_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
- MSR_NEHALEM_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
- MSR_NEHALEM_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
- MSR_NEHALEM_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_MC3_CTL 0x0000040C\r
-#define MSR_NEHALEM_MC4_CTL 0x00000410\r
-#define MSR_NEHALEM_MC5_CTL 0x00000414\r
-#define MSR_NEHALEM_MC6_CTL 0x00000418\r
-#define MSR_NEHALEM_MC7_CTL 0x0000041C\r
-#define MSR_NEHALEM_MC8_CTL 0x00000420\r
-#define MSR_NEHALEM_MC9_CTL 0x00000424\r
-#define MSR_NEHALEM_MC10_CTL 0x00000428\r
-#define MSR_NEHALEM_MC11_CTL 0x0000042C\r
-#define MSR_NEHALEM_MC12_CTL 0x00000430\r
-#define MSR_NEHALEM_MC13_CTL 0x00000434\r
-#define MSR_NEHALEM_MC14_CTL 0x00000438\r
-#define MSR_NEHALEM_MC15_CTL 0x0000043C\r
-#define MSR_NEHALEM_MC16_CTL 0x00000440\r
-#define MSR_NEHALEM_MC17_CTL 0x00000444\r
-#define MSR_NEHALEM_MC18_CTL 0x00000448\r
-#define MSR_NEHALEM_MC19_CTL 0x0000044C\r
-#define MSR_NEHALEM_MC20_CTL 0x00000450\r
-#define MSR_NEHALEM_MC21_CTL 0x00000454\r
-/// @}\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.\r
-\r
- @param ECX MSR_NEHALEM_MCi_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
- MSR_NEHALEM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
- MSR_NEHALEM_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
- MSR_NEHALEM_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
- MSR_NEHALEM_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
- MSR_NEHALEM_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
- MSR_NEHALEM_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
- MSR_NEHALEM_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
- MSR_NEHALEM_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
- MSR_NEHALEM_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
- MSR_NEHALEM_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
- MSR_NEHALEM_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
- MSR_NEHALEM_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
- MSR_NEHALEM_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
- MSR_NEHALEM_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
- MSR_NEHALEM_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
- MSR_NEHALEM_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
- MSR_NEHALEM_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
- MSR_NEHALEM_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_MC3_STATUS 0x0000040D\r
-#define MSR_NEHALEM_MC4_STATUS 0x00000411\r
-#define MSR_NEHALEM_MC5_STATUS 0x00000415\r
-#define MSR_NEHALEM_MC6_STATUS 0x00000419\r
-#define MSR_NEHALEM_MC7_STATUS 0x0000041D\r
-#define MSR_NEHALEM_MC8_STATUS 0x00000421\r
-#define MSR_NEHALEM_MC9_STATUS 0x00000425\r
-#define MSR_NEHALEM_MC10_STATUS 0x00000429\r
-#define MSR_NEHALEM_MC11_STATUS 0x0000042D\r
-#define MSR_NEHALEM_MC12_STATUS 0x00000431\r
-#define MSR_NEHALEM_MC13_STATUS 0x00000435\r
-#define MSR_NEHALEM_MC14_STATUS 0x00000439\r
-#define MSR_NEHALEM_MC15_STATUS 0x0000043D\r
-#define MSR_NEHALEM_MC16_STATUS 0x00000441\r
-#define MSR_NEHALEM_MC17_STATUS 0x00000445\r
-#define MSR_NEHALEM_MC18_STATUS 0x00000449\r
-#define MSR_NEHALEM_MC19_STATUS 0x0000044D\r
-#define MSR_NEHALEM_MC20_STATUS 0x00000451\r
-#define MSR_NEHALEM_MC21_STATUS 0x00000455\r
-/// @}\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs."\r
-\r
- The MSR_MC3_ADDR register is either not implemented or contains no address\r
- if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not\r
- implemented in the processor, all reads and writes to this MSR will cause a\r
- general-protection exception.\r
-\r
- The MSR_MC4_ADDR register is either not implemented or contains no address\r
- if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not\r
- implemented in the processor, all reads and writes to this MSR will cause a\r
- general-protection exception.\r
-\r
- @param ECX MSR_NEHALEM_MC3_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_NEHALEM_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
- MSR_NEHALEM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
- MSR_NEHALEM_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
- MSR_NEHALEM_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
- MSR_NEHALEM_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
- MSR_NEHALEM_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
- MSR_NEHALEM_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
- MSR_NEHALEM_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
- MSR_NEHALEM_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
- MSR_NEHALEM_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
- MSR_NEHALEM_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
- MSR_NEHALEM_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
- MSR_NEHALEM_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
- MSR_NEHALEM_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
- MSR_NEHALEM_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
- MSR_NEHALEM_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
- MSR_NEHALEM_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
- MSR_NEHALEM_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
- MSR_NEHALEM_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_MC3_ADDR 0x0000040E\r
-#define MSR_NEHALEM_MC4_ADDR 0x00000412\r
-#define MSR_NEHALEM_MC5_ADDR 0x00000416\r
-#define MSR_NEHALEM_MC6_ADDR 0x0000041A\r
-#define MSR_NEHALEM_MC7_ADDR 0x0000041E\r
-#define MSR_NEHALEM_MC8_ADDR 0x00000422\r
-#define MSR_NEHALEM_MC9_ADDR 0x00000426\r
-#define MSR_NEHALEM_MC10_ADDR 0x0000042A\r
-#define MSR_NEHALEM_MC11_ADDR 0x0000042E\r
-#define MSR_NEHALEM_MC12_ADDR 0x00000432\r
-#define MSR_NEHALEM_MC13_ADDR 0x00000436\r
-#define MSR_NEHALEM_MC14_ADDR 0x0000043A\r
-#define MSR_NEHALEM_MC15_ADDR 0x0000043E\r
-#define MSR_NEHALEM_MC16_ADDR 0x00000442\r
-#define MSR_NEHALEM_MC17_ADDR 0x00000446\r
-#define MSR_NEHALEM_MC18_ADDR 0x0000044A\r
-#define MSR_NEHALEM_MC19_ADDR 0x0000044E\r
-#define MSR_NEHALEM_MC20_ADDR 0x00000452\r
-#define MSR_NEHALEM_MC21_ADDR 0x00000456\r
-/// @}\r
-\r
-\r
/**\r
Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
- branch record registers on the last branch record stack. This part of the\r
- stack contains pointers to the source instruction for one of the last\r
- sixteen branches, exceptions, or interrupts taken by the processor. See\r
- also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR\r
- Stack.".\r
+ branch record registers on the last branch record stack. The From_IP part of\r
+ the stack contains pointers to the source instruction. See also: - Last\r
+ Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in\r
+ Section 17.4.8.1.\r
\r
@param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP\r
@param EAX Lower 32-bits of MSR value.\r
/**\r
Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction for one of the last sixteen\r
- branches, exceptions, or interrupts taken by the processor.\r
+ contains pointers to the destination instruction.\r
\r
@param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)\r
\r
\r
/**\r
- Package. See Section 18.7.2.3, "Uncore Address/Opcode Match MSR.".\r
+ Package. See Section 18.8.2.3, "Uncore Address/Opcode Match MSR.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. See Section 18.7.2.2, "Uncore Performance Event Configuration\r
+ Package. See Section 18.8.2.2, "Uncore Performance Event Configuration\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PMCi\r
/// @}\r
\r
/**\r
- Package. See Section 18.7.2.2, "Uncore Performance Event Configuration\r
+ Package. See Section 18.8.2.2, "Uncore Performance Event Configuration\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.21.\r
\r
**/\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.".\r
+ See Section 35.22, "MSRs in Pentium Processors.".\r
\r
@param ECX MSR_P6_P5_MC_ADDR (0x00000000)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.".\r
+ See Section 35.22, "MSRs in Pentium Processors.".\r
\r
@param ECX MSR_P6_P5_MC_TYPE (0x00000001)\r
@param EAX Lower 32-bits of MSR value.\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.18.\r
\r
**/\r
\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] PEBS_UNAVILABLE: Precise Event Based Sampling Unavailable (R)\r
- /// See Table 35-2. When set, the processor does not support precise\r
+ /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable\r
+ /// (R) See Table 35-2. When set, the processor does not support processor\r
/// event-based sampling (PEBS); when clear, PEBS is supported.\r
///\r
UINT32 PEBS:1;\r
0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains\r
a pointer to the last branch instruction that the processor executed prior\r
to the last exception that was generated or the last interrupt that was\r
- handled. See Section 17.10.3, "Last Exception Records.". Unique. From Linear\r
+ handled. See Section 17.11.3, "Last Exception Records.". Unique. From Linear\r
IP Linear address of the last branch instruction (If IA32e mode is active).\r
From Linear IP Linear address of the last branch instruction. Reserved.\r
\r
0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area\r
contains a pointer to the target of the last branch instruction that the\r
processor executed prior to the last exception that was generated or the\r
- last interrupt that was handled. See Section 17.10.3, "Last Exception\r
+ last interrupt that was handled. See Section 17.11.3, "Last Exception\r
Records.". Unique. From Linear IP Linear address of the target of the last\r
branch instruction (If IA-32e mode is active). From Linear IP Linear address\r
of the target of the last branch instruction. Reserved.\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug\r
features are used. Bit definitions are discussed in the referenced section.\r
- See Section 17.10.1, "MSR_DEBUGCTLA MSR.".\r
+ See Section 17.11.1, "MSR_DEBUGCTLA MSR.".\r
\r
@param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)\r
@param EAX Lower 32-bits of MSR value.\r
0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an\r
index (0-3 or 0-15) that points to the top of the last branch record stack\r
(that is, that points the index of the MSR containing the most recent branch\r
- record). See Section 17.10.2, "LBR Stack for Processors Based on Intel\r
+ record). See Section 17.11.2, "LBR Stack for Processors Based on Intel\r
NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.\r
\r
@param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)\r
exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through\r
MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models\r
0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See\r
- Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
+ Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
for Processors based on Skylake Microarchitecture.".\r
\r
@param ECX MSR_PENTIUM_4_LASTBRANCH_n\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".\r
\r
@param ECX MSR_PENTIUM_4_BPU_COUNTERn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".\r
\r
@param ECX MSR_PENTIUM_4_MS_COUNTERn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".\r
\r
@param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".\r
\r
@param ECX MSR_PENTIUM_4_IQ_COUNTERn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BPU_CCCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MS_CCCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FLAME_CCCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IQ_CCCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available\r
+ 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available\r
on later processors. It is only available on processor family 0FH, models\r
01H-02H.\r
\r
\r
\r
/**\r
- 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available\r
+ 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available\r
on later processors. It is only available on processor family 0FH, models\r
01H-02H.\r
\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_ALF_ESCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. Precise Event-Based Sampling (PEBS) (R/W)\r
- Controls the enabling of precise event sampling and replay tagging.\r
+ 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)\r
+ Controls the enabling of processor event sampling and replay tagging.\r
\r
@param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bits 12:0] See Table 19-26.\r
+ /// [Bits 12:0] See Table 19-33.\r
///\r
UINT32 EventNum:13;\r
UINT32 Reserved1:11;\r
///\r
/// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical\r
/// processor when set; disables PEBS when clear (default). See Section\r
- /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
+ /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
/// logical processor. This bit is called ENABLE_PEBS in IA-32 processors\r
/// that do not support Intel HyperThreading Technology.\r
///\r
///\r
/// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical\r
/// processor when set; disables PEBS when clear (default). See Section\r
- /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
+ /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
/// logical processor. This bit is reserved for IA-32 processors that do\r
/// not support Intel Hyper-Threading Technology.\r
///\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Table 19-26.\r
+ 0, 1, 2, 3, 4, 6. Shared. See Table 19-33.\r
\r
@param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)\r
@param EAX Lower 32-bits of MSR value.\r
680H-68FH, 6C0H-6CfH are not available in processor releases before family\r
0FH, model 03H. These MSRs replace MSRs previously located at\r
1DBH-1DEH.which performed the same function for early releases. See Section\r
- 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording for\r
+ 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording for\r
Processors based on Skylake Microarchitecture.".\r
\r
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP\r
record registers on the last branch record stack (6C0H-6CFH). This part of\r
the stack contains pointers to the destination instruction for one of the\r
last 16 branches, exceptions, or interrupts that the processor took. See\r
- Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
+ Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
for Processors based on Skylake Microarchitecture.".\r
\r
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP\r
\r
/**\r
3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See\r
- Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
+ Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
with Up to 8-MByte L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)\r
\r
/**\r
3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See\r
- Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
+ Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
with Up to 8-MByte L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)\r
\r
/**\r
3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See\r
- Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
+ Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
with Up to 8-MByte L3 Cache" for details.\r
\r
@param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)\r
\r
\r
/**\r
- 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.17,\r
+ 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.21,\r
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
L3 Cache" for details.\r
\r
\r
\r
/**\r
- 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.17,\r
+ 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.21,\r
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
L3 Cache.".\r
\r
\r
\r
/**\r
- 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.17,\r
+ 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.21,\r
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
L3 Cache.".\r
\r
\r
/**\r
6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r
- 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
+ 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
8-MByte L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)\r
\r
\r
/**\r
- 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.17,\r
+ 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.21,\r
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
L3 Cache" for details.\r
\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.20.\r
\r
**/\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.".\r
+ See Section 35.22, "MSRs in Pentium Processors.".\r
\r
@param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.".\r
+ See Section 35.22, "MSRs in Pentium Processors.".\r
\r
@param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)\r
@param EAX Lower 32-bits of MSR value.\r
Last Branch Record n (R/W) One of 8 last branch record registers on the last\r
branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold\r
the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section\r
- 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
+ 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
Processors)".\r
\r
@param ECX MSR_PENTIUM_M_LASTBRANCH_n\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Precise Event Based Sampling Unavailable (RO) 1 = Processor\r
- /// does not support precise event-based sampling (PEBS); 0 = PEBS is\r
- /// supported. The Pentium M processor does not support PEBS.\r
+ /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =\r
+ /// Processor does not support processor event based sampling (PEBS); 0 =\r
+ /// PEBS is supported. The Pentium M processor does not support PEBS.\r
///\r
UINT32 PEBS:1;\r
UINT32 Reserved5:3;\r
/**\r
Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points\r
to the MSR containing the most recent branch record. See also: -\r
- MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.12, "Last Branch, Interrupt,\r
+ MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,\r
and Exception Recording (Pentium M Processors)".\r
\r
@param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)\r
\r
/**\r
Debug Control (R/W) Controls how several debug features are used. Bit\r
- definitions are discussed in the referenced section. See Section 17.12,\r
+ definitions are discussed in the referenced section. See Section 17.13,\r
"Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".\r
\r
@param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)\r
Last Exception Record To Linear IP (R) This area contains a pointer to the\r
target of the last branch instruction that the processor executed prior to\r
the last exception that was generated or the last interrupt that was\r
- handled. See Section 17.12, "Last Branch, Interrupt, and Exception Recording\r
- (Pentium M Processors)" and Section 17.13.2, "Last Branch and Last Exception\r
+ handled. See Section 17.13, "Last Branch, Interrupt, and Exception Recording\r
+ (Pentium M Processors)" and Section 17.14.2, "Last Branch and Last Exception\r
MSRs.".\r
\r
@param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)\r
Last Exception Record From Linear IP (R) Contains a pointer to the last\r
branch instruction that the processor executed prior to the last exception\r
that was generated or the last interrupt that was handled. See Section\r
- 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
- Processors)" and Section 17.13.2, "Last Branch and Last Exception MSRs.".\r
+ 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
+ Processors)" and Section 17.14.2, "Last Branch and Last Exception MSRs.".\r
\r
@param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)\r
@param EAX Lower 32-bits of MSR value.\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.22.\r
\r
**/\r
\r
\r
\r
/**\r
- See Section 17.14, "Time-Stamp Counter.".\r
+ See Section 17.15, "Time-Stamp Counter.".\r
\r
@param ECX MSR_PENTIUM_TSC (0x00000010)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 18.20.1, "Control and Event Select Register (CESR).".\r
+ See Section 18.24.1, "Control and Event Select Register (CESR).".\r
\r
@param ECX MSR_PENTIUM_CESR (0x00000011)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Section 18.20.3, "Events Counted.".\r
+ Section 18.24.3, "Events Counted.".\r
\r
@param ECX MSR_PENTIUM_CTRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.9.\r
\r
**/\r
\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See\r
+ /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 35-2.\r
///\r
UINT32 PEBS:1;\r
\r
/**\r
Thread. Last Branch Record Filtering Select Register (R/W) See Section\r
- 17.6.2, "Filtering of Last Branch Records.".\r
+ 17.7.2, "Filtering of Last Branch Records.".\r
\r
@param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)\r
@param EAX Lower 32-bits of MSR value.\r
/**\r
Package. Always 0 (CMCI not supported).\r
\r
- @param ECX MSR_SANDY_BRIDGE_MC4_CTL2 (0x00000284)\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2, Msr);\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);\r
@endcode\r
- @note MSR_SANDY_BRIDGE_MC4_CTL2 is defined as MSR_MC4_CTL2 in SDM.\r
+ @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_MC4_CTL2 0x00000284\r
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284\r
\r
\r
/**\r
See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".\r
\r
- @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
@param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;\r
+ MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
@endcode\r
- @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
+ @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
MSR information returned for MSR index\r
- #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS\r
+ #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
///\r
/// All bit fields as a 64-bit value\r
///\r
UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER;\r
+} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
\r
/**\r
\r
\r
/**\r
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".\r
+ Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".\r
\r
@param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Thread. see See Section 18.7.1.2, "Load Latency Performance Monitoring\r
+ Thread. see See Section 18.8.1.2, "Load Latency Performance Monitoring\r
Facility.".\r
\r
@param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)\r
/**\r
Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
\r
- @param ECX MSR_SANDY_BRIDGE_MC4_CTL (0x00000410)\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)\r
@param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- MSR_SANDY_BRIDGE_MC4_CTL_REGISTER Msr;\r
+ MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;\r
\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL, Msr.Uint64);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);\r
@endcode\r
- @note MSR_SANDY_BRIDGE_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
+ @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_MC4_CTL 0x00000410\r
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410\r
\r
/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_MC4_CTL\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL\r
**/\r
typedef union {\r
///\r
/// All bit fields as a 64-bit value\r
///\r
UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_MC4_CTL_REGISTER;\r
+} MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER;\r
\r
\r
/**\r
Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
branch record registers on the last branch record stack. This part of the\r
stack contains pointers to the source instruction. See also: - Last Branch\r
- Record Stack TOS at 1C9H - Section 17.6.1, "LBR Stack.".\r
+ Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section\r
+ 17.4.8.1.\r
\r
@param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bit 0] Core 0 select.\r
+ /// [Bit 0] Slice 0 select.\r
///\r
- UINT32 PMI_Sel_Core0:1;\r
+ UINT32 PMI_Sel_Slice0:1;\r
///\r
- /// [Bit 1] Core 1 select.\r
+ /// [Bit 1] Slice 1 select.\r
///\r
- UINT32 PMI_Sel_Core1:1;\r
+ UINT32 PMI_Sel_Slice1:1;\r
///\r
- /// [Bit 2] Core 2 select.\r
+ /// [Bit 2] Slice 2 select.\r
///\r
- UINT32 PMI_Sel_Core2:1;\r
+ UINT32 PMI_Sel_Slice2:1;\r
///\r
- /// [Bit 3] Core 3 select.\r
+ /// [Bit 3] Slice 3 select.\r
///\r
- UINT32 PMI_Sel_Core3:1;\r
- UINT32 Reserved1:15;\r
+ UINT32 PMI_Sel_Slice3:1;\r
+ ///\r
+ /// [Bit 4] Slice 4 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice4:1;\r
+ UINT32 Reserved1:14;\r
UINT32 Reserved2:10;\r
///\r
/// [Bit 29] Enable all uncore counters.\r
///\r
struct {\r
///\r
- /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".\r
+ /// [Bits 3:0] Report the number of C-Box units with performance counters,\r
+ /// including processor cores and processor graphics".\r
///\r
UINT32 CBox:4;\r
UINT32 Reserved1:28;\r
\r
\r
/**\r
- Package. Uncore C-Box 0, counter 0 event select MSR.\r
+ Package. Uncore C-Box 0, counter n event select MSR.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.\r
+ @{\r
**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 0, counter 1 event select MSR.\r
+ Package. Uncore C-Box n, unit status for counter 0-3.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1, Msr);\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);\r
@endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.\r
+ @{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 0, performance counter 0.\r
+ Package. Uncore C-Box 0, performance counter n.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 (0x00000706)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.\r
+ @{\r
**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, performance counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 (0x00000707)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
-**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 1, counter 0 event select MSR.\r
+ Package. Uncore C-Box 1, counter n event select MSR.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.\r
+ @{\r
**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, counter 1 event select MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
-**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 1, performance counter 0.\r
+ Package. Uncore C-Box 1, performance counter n.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 (0x00000716)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.\r
+ @{\r
**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, performance counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 (0x00000717)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
-**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 2, counter 0 event select MSR.\r
+ Package. Uncore C-Box 2, counter n event select MSR.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.\r
+ @{\r
**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, counter 1 event select MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
-**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 2, performance counter 0.\r
+ Package. Uncore C-Box 2, performance counter n.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 (0x00000726)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.\r
+ @{\r
**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, performance counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 (0x00000727)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
-**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 3, counter 0 event select MSR.\r
+ Package. Uncore C-Box 3, counter n event select MSR.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.\r
+ @{\r
**/\r
#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 3, counter 1 event select MSR.\r
+ Package. Uncore C-Box 3, performance counter n.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1, Msr);\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);\r
@endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.\r
+ @{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 3, performance counter 0.\r
+ Package. Uncore C-Box 4, counter n event select MSR.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 (0x00000736)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);\r
@endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.\r
+ @{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743\r
+/// @}\r
\r
\r
/**\r
- Package. Uncore C-Box 3, performance counter 1.\r
+ Package. Uncore C-Box 4, performance counter n.\r
\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 (0x00000737)\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1, Msr);\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);\r
@endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.\r
+ @{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749\r
+/// @}\r
\r
\r
/**\r
///\r
/// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS\r
/// counting logic for specific events requiring additional configuration,\r
- /// see Table 19-9.\r
+ /// see Table 19-15.\r
///\r
UINT32 ENABLE_PEBS_NUM_ALT:1;\r
UINT32 Reserved1:31;\r
} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;\r
\r
\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
- MSR_SANDY_BRIDGE_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_MC5_CTL 0x00000414\r
-#define MSR_SANDY_BRIDGE_MC6_CTL 0x00000418\r
-#define MSR_SANDY_BRIDGE_MC7_CTL 0x0000041C\r
-#define MSR_SANDY_BRIDGE_MC8_CTL 0x00000420\r
-#define MSR_SANDY_BRIDGE_MC9_CTL 0x00000424\r
-#define MSR_SANDY_BRIDGE_MC10_CTL 0x00000428\r
-#define MSR_SANDY_BRIDGE_MC11_CTL 0x0000042C\r
-#define MSR_SANDY_BRIDGE_MC12_CTL 0x00000430\r
-#define MSR_SANDY_BRIDGE_MC13_CTL 0x00000434\r
-#define MSR_SANDY_BRIDGE_MC14_CTL 0x00000438\r
-#define MSR_SANDY_BRIDGE_MC15_CTL 0x0000043C\r
-#define MSR_SANDY_BRIDGE_MC16_CTL 0x00000440\r
-#define MSR_SANDY_BRIDGE_MC17_CTL 0x00000444\r
-#define MSR_SANDY_BRIDGE_MC18_CTL 0x00000448\r
-#define MSR_SANDY_BRIDGE_MC19_CTL 0x0000044C\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_MCi_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_MC5_STATUS 0x00000415\r
-#define MSR_SANDY_BRIDGE_MC6_STATUS 0x00000419\r
-#define MSR_SANDY_BRIDGE_MC7_STATUS 0x0000041D\r
-#define MSR_SANDY_BRIDGE_MC8_STATUS 0x00000421\r
-#define MSR_SANDY_BRIDGE_MC9_STATUS 0x00000425\r
-#define MSR_SANDY_BRIDGE_MC10_STATUS 0x00000429\r
-#define MSR_SANDY_BRIDGE_MC11_STATUS 0x0000042D\r
-#define MSR_SANDY_BRIDGE_MC12_STATUS 0x00000431\r
-#define MSR_SANDY_BRIDGE_MC13_STATUS 0x00000435\r
-#define MSR_SANDY_BRIDGE_MC14_STATUS 0x00000439\r
-#define MSR_SANDY_BRIDGE_MC15_STATUS 0x0000043D\r
-#define MSR_SANDY_BRIDGE_MC16_STATUS 0x00000441\r
-#define MSR_SANDY_BRIDGE_MC17_STATUS 0x00000445\r
-#define MSR_SANDY_BRIDGE_MC18_STATUS 0x00000449\r
-#define MSR_SANDY_BRIDGE_MC19_STATUS 0x0000044D\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_MCi_ADDR\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
- MSR_SANDY_BRIDGE_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_MC5_ADDR 0x00000416\r
-#define MSR_SANDY_BRIDGE_MC6_ADDR 0x0000041A\r
-#define MSR_SANDY_BRIDGE_MC7_ADDR 0x0000041E\r
-#define MSR_SANDY_BRIDGE_MC8_ADDR 0x00000422\r
-#define MSR_SANDY_BRIDGE_MC9_ADDR 0x00000426\r
-#define MSR_SANDY_BRIDGE_MC10_ADDR 0x0000042A\r
-#define MSR_SANDY_BRIDGE_MC11_ADDR 0x0000042E\r
-#define MSR_SANDY_BRIDGE_MC12_ADDR 0x00000432\r
-#define MSR_SANDY_BRIDGE_MC13_ADDR 0x00000436\r
-#define MSR_SANDY_BRIDGE_MC14_ADDR 0x0000043A\r
-#define MSR_SANDY_BRIDGE_MC15_ADDR 0x0000043E\r
-#define MSR_SANDY_BRIDGE_MC16_ADDR 0x00000442\r
-#define MSR_SANDY_BRIDGE_MC17_ADDR 0x00000446\r
-#define MSR_SANDY_BRIDGE_MC18_ADDR 0x0000044A\r
-#define MSR_SANDY_BRIDGE_MC19_ADDR 0x0000044E\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_MCi_MISC\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_MISC);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_MISC, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
- MSR_SANDY_BRIDGE_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_MC5_MISC 0x00000417\r
-#define MSR_SANDY_BRIDGE_MC6_MISC 0x0000041B\r
-#define MSR_SANDY_BRIDGE_MC7_MISC 0x0000041F\r
-#define MSR_SANDY_BRIDGE_MC8_MISC 0x00000423\r
-#define MSR_SANDY_BRIDGE_MC9_MISC 0x00000427\r
-#define MSR_SANDY_BRIDGE_MC10_MISC 0x0000042B\r
-#define MSR_SANDY_BRIDGE_MC11_MISC 0x0000042F\r
-#define MSR_SANDY_BRIDGE_MC12_MISC 0x00000433\r
-#define MSR_SANDY_BRIDGE_MC13_MISC 0x00000437\r
-#define MSR_SANDY_BRIDGE_MC14_MISC 0x0000043B\r
-#define MSR_SANDY_BRIDGE_MC15_MISC 0x0000043F\r
-#define MSR_SANDY_BRIDGE_MC16_MISC 0x00000443\r
-#define MSR_SANDY_BRIDGE_MC17_MISC 0x00000447\r
-#define MSR_SANDY_BRIDGE_MC18_MISC 0x0000044B\r
-#define MSR_SANDY_BRIDGE_MC19_MISC 0x0000044F\r
-/// @}\r
-\r
-\r
/**\r
Package. Package RAPL Perf Status (R/O).\r
\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.4.\r
\r
**/\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
- Shared. Model Specific Platform ID (R).\r
+ Module. Model Specific Platform ID (R).\r
\r
@param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
- processor features; (R) indicates current processor configuration.\r
+ Module. Processor Hard Power-On Configuration (R/W) Writes ignored.\r
\r
@param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)\r
@param EAX Lower 32-bits of MSR value.\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
- /// Always 0.\r
- ///\r
- UINT32 DataErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
- /// Always 0.\r
- ///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
- ///\r
- UINT32 AERR_DriveEnable:1;\r
- ///\r
- /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =\r
- /// Disabled Always 0.\r
- ///\r
- UINT32 BERR_Enable:1;\r
- UINT32 Reserved2:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
- ///\r
- UINT32 BINIT_DriverEnable:1;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 ExecuteBIST:1;\r
- ///\r
- /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
- /// Always 0.\r
- ///\r
- UINT32 AERR_ObservationEnabled:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
- /// Always 0.\r
- ///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
- ///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved7:1;\r
- ///\r
- /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.\r
- ///\r
- UINT32 APICClusterID:2;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.\r
- ///\r
- UINT32 SymmetricArbitrationID:2;\r
- ///\r
- /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
- ///\r
- UINT32 IntegerBusFrequencyRatio:5;\r
- UINT32 Reserved9:5;\r
- UINT32 Reserved10:32;\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
} MSR_SILVERMONT_SMI_COUNT_REGISTER;\r
\r
\r
+/**\r
+ Core. Control Features in Intel 64 Processor (R/W). See Table 35-2.\r
+\r
+ @param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type\r
+ MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type\r
+ MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Lock (R/WL).\r
+ ///\r
+ UINT32 Lock:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] Enable VMX outside SMX operation (R/WL).\r
+ ///\r
+ UINT32 EnableVmxOutsideSmx:1;\r
+ UINT32 Reserved2:29;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
/**\r
Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the source instruction for one of the last eight\r
- branches, exceptions, or interrupts taken by the processor. See also: -\r
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,\r
- Interrupt, and Exception Recording (Pentium M Processors).".\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction. See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.5 and record format in Section\r
+ 17.4.8.1.\r
\r
@param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP\r
@param EAX Lower 32-bits of MSR value.\r
\r
/**\r
Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction for one of the last eight\r
- branches, exceptions, or interrupts taken by the processor.\r
+ record registers on the last branch record stack. The To_IP part of the\r
+ stack contains pointers to the destination instruction.\r
\r
@param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
+ Module. Scalable Bus Speed(RO) This field indicates the intended scalable\r
bus clock speed for processors based on Silvermont microarchitecture:.\r
\r
@param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)\r
\r
\r
/**\r
- Shared. C-State Configuration Control (R/W) Note: C-state values are\r
+ Module. C-State Configuration Control (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
parameters or ACPI CStates. See http://biosbits.org.\r
\r
\r
\r
/**\r
- Shared. Power Management IO Redirection in C-state (R/W) See\r
+ Module. Power Management IO Redirection in C-state (R/W) See\r
http://biosbits.org.\r
\r
@param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)\r
\r
\r
/**\r
- Shared.\r
+ Module.\r
\r
@param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)\r
@param EAX Lower 32-bits of MSR value.\r
UINT32 FastStrings:1;\r
UINT32 Reserved1:2;\r
///\r
- /// [Bit 3] Shared. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 35-2.\r
+ /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See\r
+ /// Table 35-2. Default value is 0.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Core. Precise Event Based Sampling Unavailable (RO) See Table\r
- /// 35-2.\r
+ /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
+ /// Table 35-2.\r
///\r
UINT32 PEBS:1;\r
UINT32 Reserved4:3;\r
///\r
- /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
+ /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 35-2.\r
///\r
UINT32 EIST:1;\r
///\r
UINT32 LimitCpuidMaxval:1;\r
///\r
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r
+ /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 35-2.\r
///\r
UINT32 xTPR_Message_Disable:1;\r
UINT32 Reserved7:8;\r
UINT32 XD:1;\r
UINT32 Reserved9:3;\r
///\r
- /// [Bit 38] Shared. Turbo Mode Disable (R/W) When set to 1 on processors\r
+ /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors\r
/// that support Intel Turbo Boost Technology, the turbo mode feature is\r
/// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
/// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
\r
\r
/**\r
- Shared. Offcore Response Event Select Register (R/W).\r
+ Miscellaneous Feature Control (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L2 hardware prefetcher, which fetches additional lines of code or data\r
+ /// into the L2 cache.\r
+ ///\r
+ UINT32 L2HardwarePrefetcherDisable:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
+ /// the L1 data cache prefetcher, which fetches the next cache line into\r
+ /// L1 data cache.\r
+ ///\r
+ UINT32 DCUHardwarePrefetcherDisable:1;\r
+ UINT32 Reserved2:29;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Module. Offcore Response Event Select Register (R/W).\r
\r
@param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Shared. Offcore Response Event Select Register (R/W).\r
+ Module. Offcore Response Event Select Register (R/W).\r
\r
@param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)\r
@param EAX Lower 32-bits of MSR value.\r
} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;\r
\r
\r
+/**\r
+ Core. Last Branch Record Filtering Select Register (R/W) See Section\r
+ 17.7.2, "Filtering of Last Branch Records.".\r
+\r
+ @param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_LBR_SELECT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
+**/\r
+#define MSR_SILVERMONT_LBR_SELECT 0x000001C8\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CPL_EQ_0.\r
+ ///\r
+ UINT32 CPL_EQ_0:1;\r
+ ///\r
+ /// [Bit 1] CPL_NEQ_0.\r
+ ///\r
+ UINT32 CPL_NEQ_0:1;\r
+ ///\r
+ /// [Bit 2] JCC.\r
+ ///\r
+ UINT32 JCC:1;\r
+ ///\r
+ /// [Bit 3] NEAR_REL_CALL.\r
+ ///\r
+ UINT32 NEAR_REL_CALL:1;\r
+ ///\r
+ /// [Bit 4] NEAR_IND_CALL.\r
+ ///\r
+ UINT32 NEAR_IND_CALL:1;\r
+ ///\r
+ /// [Bit 5] NEAR_RET.\r
+ ///\r
+ UINT32 NEAR_RET:1;\r
+ ///\r
+ /// [Bit 6] NEAR_IND_JMP.\r
+ ///\r
+ UINT32 NEAR_IND_JMP:1;\r
+ ///\r
+ /// [Bit 7] NEAR_REL_JMP.\r
+ ///\r
+ UINT32 NEAR_REL_JMP:1;\r
+ ///\r
+ /// [Bit 8] FAR_BRANCH.\r
+ ///\r
+ UINT32 FAR_BRANCH:1;\r
+ UINT32 Reserved1:23;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_LBR_SELECT_REGISTER;\r
+\r
+\r
/**\r
Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that\r
points to the MSR containing the most recent branch record. See\r
- MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
+ MSR_LASTBRANCH_0_FROM_IP.\r
\r
@param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Core. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
- Facilities.".\r
-\r
- @param ECX MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
-**/\r
-#define MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
-/**\r
- Core. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling\r
+ Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r
(PEBS).".\r
\r
@param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)\r
///\r
struct {\r
///\r
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
+ /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).\r
///\r
UINT32 PEBS:1;\r
UINT32 Reserved1:31;\r
#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r
\r
\r
-/**\r
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_SILVERMONT_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_CTL);\r
- AsmWriteMsr64 (MSR_SILVERMONT_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
- MSR_SILVERMONT_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
- MSR_SILVERMONT_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_SILVERMONT_MC3_CTL 0x0000040C\r
-#define MSR_SILVERMONT_MC4_CTL 0x00000410\r
-#define MSR_SILVERMONT_MC5_CTL 0x00000414\r
-/// @}\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_SILVERMONT_MCi_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_SILVERMONT_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
- MSR_SILVERMONT_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
- MSR_SILVERMONT_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_SILVERMONT_MC3_STATUS 0x0000040D\r
-#define MSR_SILVERMONT_MC4_STATUS 0x00000411\r
-#define MSR_SILVERMONT_MC5_STATUS 0x00000415\r
-/// @}\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MCi_ADDR register\r
- is either not implemented or contains no address if the ADDRV flag in the\r
- MSR_MCi_STATUS register is clear. When not implemented in the processor, all\r
- reads and writes to this MSR will cause a general-protection exception.\r
-\r
- @param ECX MSR_SILVERMONT_MCi_ADDR\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_SILVERMONT_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
- MSR_SILVERMONT_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
- MSR_SILVERMONT_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_SILVERMONT_MC3_ADDR 0x0000040E\r
-#define MSR_SILVERMONT_MC4_ADDR 0x00000412\r
-#define MSR_SILVERMONT_MC5_ADDR 0x00000416\r
-/// @}\r
-\r
-\r
/**\r
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
\r
struct {\r
///\r
/// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package\r
- /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-7.\r
+ /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-8.\r
///\r
UINT32 Limit:15;\r
///\r
\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."\r
- and MSR_RAPL_POWER_UNIT in Table 35-7.\r
+ and MSR_RAPL_POWER_UNIT in Table 35-8.\r
\r
@param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)\r
@param EAX Lower 32-bits of MSR value.\r
\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.\r
+ Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.\r
\r
@param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)\r
@param EAX Lower 32-bits of MSR value.\r
struct {\r
///\r
/// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
- /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.\r
+ /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.\r
///\r
UINT32 Limit:15;\r
///\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.7.\r
\r
**/\r
\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.14.\r
\r
**/\r
\r
///\r
struct {\r
///\r
- /// [Bit 0] LockOut (R/WO) See Table 35-21.\r
+ /// [Bit 0] LockOut (R/WO) See Table 35-24.\r
///\r
UINT32 LockOut:1;\r
///\r
- /// [Bit 1] Enable_PPIN (R/W) See Table 35-21.\r
+ /// [Bit 1] Enable_PPIN (R/W) See Table 35-24.\r
///\r
UINT32 Enable_PPIN:1;\r
UINT32 Reserved1:30;\r
\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
- Inventory Number (R/O) See Table 35-21.\r
+ Inventory Number (R/O) See Table 35-24.\r
\r
@param ECX MSR_XEON_D_PPIN (0x0000004F)\r
@param EAX Lower 32-bits of MSR value.\r
struct {\r
UINT32 Reserved1:8;\r
///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-21.\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-24.\r
///\r
UINT32 MaximumNonTurboRatio:8;\r
UINT32 Reserved2:7;\r
///\r
- /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-21.\r
+ /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-24.\r
///\r
UINT32 PPIN_CAP:1;\r
UINT32 Reserved3:4;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
- /// Table 35-21.\r
+ /// Table 35-24.\r
///\r
UINT32 RatioLimit:1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
- /// Table 35-21.\r
+ /// Table 35-24.\r
///\r
UINT32 TDPLimit:1;\r
///\r
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-21.\r
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-24.\r
///\r
UINT32 TJOFFSET:1;\r
UINT32 Reserved4:1;\r
UINT32 Reserved5:8;\r
///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-21.\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-24.\r
///\r
UINT32 MaximumEfficiencyRatio:8;\r
UINT32 Reserved6:16;\r
struct {\r
UINT32 Reserved1:16;\r
///\r
- /// [Bits 23:16] Temperature Target (RO) See Table 35-21.\r
+ /// [Bits 23:16] Temperature Target (RO) See Table 35-24.\r
///\r
UINT32 TemperatureTarget:8;\r
///\r
- /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-21.\r
+ /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-24.\r
///\r
UINT32 TCCActivationOffset:4;\r
UINT32 Reserved2:4;\r
\r
\r
/**\r
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+ Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
\r
@param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)\r
@param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
@endcode\r
@note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
+ /// to enable DRAM RAPL mode 0 (Direct VR).\r
+ ///\r
+ UINT32 Energy:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;\r
+\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
\r
\r
+/**\r
+ Package. Reserved (R/O) Reads return 0.\r
+\r
+ @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
refers to processor core frequency).\r
\r
/**\r
THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
- ECX=0):EBX.PQM[bit 12] = 1.\r
+ ECX=0):EBX.RDT-M[bit 12] = 1.\r
\r
@param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)\r
@param EAX Lower 32-bits of MSR value.\r
} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
\r
\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- * Bank MC5 reports MC error from the Intel QPI 0 module.\r
- * Bank MC6 reports MC error from the integrated I/O module.\r
- * Bank MC7 reports MC error from the home agent HA 0.\r
- * Bank MC8 reports MC error from the home agent HA 1.\r
- * Banks MC9 through MC16 report MC error from each channel of the integrated\r
- memory controllers.\r
- * Bank MC17 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.\r
- * Bank MC18 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.\r
- * Bank MC19 reports MC error from the following pair of CBo/L3 Slices\r
- (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.\r
- * Bank MC20 reports MC error from the Intel QPI 1 module.\r
- * Bank MC21 reports MC error from the Intel QPI 2 module.\r
-\r
- @param ECX MSR_XEON_D_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_MC5_CTL);\r
- AsmWriteMsr64 (MSR_XEON_D_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_XEON_D_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
- MSR_XEON_D_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
- MSR_XEON_D_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
- MSR_XEON_D_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
- MSR_XEON_D_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
- MSR_XEON_D_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
- MSR_XEON_D_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
- MSR_XEON_D_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
- MSR_XEON_D_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
- MSR_XEON_D_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
- MSR_XEON_D_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
- MSR_XEON_D_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
- MSR_XEON_D_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
- MSR_XEON_D_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
- MSR_XEON_D_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
- MSR_XEON_D_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
- MSR_XEON_D_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_D_MC5_CTL 0x00000414\r
-#define MSR_XEON_D_MC6_CTL 0x00000418\r
-#define MSR_XEON_D_MC7_CTL 0x0000041C\r
-#define MSR_XEON_D_MC8_CTL 0x00000420\r
-#define MSR_XEON_D_MC9_CTL 0x00000424\r
-#define MSR_XEON_D_MC10_CTL 0x00000428\r
-#define MSR_XEON_D_MC11_CTL 0x0000042C\r
-#define MSR_XEON_D_MC12_CTL 0x00000430\r
-#define MSR_XEON_D_MC13_CTL 0x00000434\r
-#define MSR_XEON_D_MC14_CTL 0x00000438\r
-#define MSR_XEON_D_MC15_CTL 0x0000043C\r
-#define MSR_XEON_D_MC16_CTL 0x00000440\r
-#define MSR_XEON_D_MC17_CTL 0x00000444\r
-#define MSR_XEON_D_MC18_CTL 0x00000448\r
-#define MSR_XEON_D_MC19_CTL 0x0000044C\r
-#define MSR_XEON_D_MC20_CTL 0x00000450\r
-#define MSR_XEON_D_MC21_CTL 0x00000454\r
-/// @}\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_XEON_D_MCi_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_D_MC6_STATUS, Msr);\r
- @endcode\r
- @note MSR_XEON_D_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
- MSR_XEON_D_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
- MSR_XEON_D_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
- MSR_XEON_D_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
- MSR_XEON_D_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
- MSR_XEON_D_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
- MSR_XEON_D_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
- MSR_XEON_D_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
- MSR_XEON_D_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
- MSR_XEON_D_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
- MSR_XEON_D_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
- MSR_XEON_D_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
- MSR_XEON_D_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
- MSR_XEON_D_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
- MSR_XEON_D_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
- MSR_XEON_D_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
- MSR_XEON_D_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_D_MC5_STATUS 0x00000415\r
-#define MSR_XEON_D_MC6_STATUS 0x00000419\r
-#define MSR_XEON_D_MC7_STATUS 0x0000041D\r
-#define MSR_XEON_D_MC8_STATUS 0x00000421\r
-#define MSR_XEON_D_MC9_STATUS 0x00000425\r
-#define MSR_XEON_D_MC10_STATUS 0x00000429\r
-#define MSR_XEON_D_MC11_STATUS 0x0000042D\r
-#define MSR_XEON_D_MC12_STATUS 0x00000431\r
-#define MSR_XEON_D_MC13_STATUS 0x00000435\r
-#define MSR_XEON_D_MC14_STATUS 0x00000439\r
-#define MSR_XEON_D_MC15_STATUS 0x0000043D\r
-#define MSR_XEON_D_MC16_STATUS 0x00000441\r
-#define MSR_XEON_D_MC17_STATUS 0x00000445\r
-#define MSR_XEON_D_MC18_STATUS 0x00000449\r
-#define MSR_XEON_D_MC19_STATUS 0x0000044D\r
-#define MSR_XEON_D_MC20_STATUS 0x00000451\r
-#define MSR_XEON_D_MC21_STATUS 0x00000455\r
-/// @}\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_XEON_D_MCi_ADDR\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_ADDR);\r
- AsmWriteMsr64 (MSR_XEON_D_MC6_ADDR, Msr);\r
- @endcode\r
- @note MSR_XEON_D_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
- MSR_XEON_D_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
- MSR_XEON_D_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
- MSR_XEON_D_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
- MSR_XEON_D_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
- MSR_XEON_D_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
- MSR_XEON_D_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
- MSR_XEON_D_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
- MSR_XEON_D_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
- MSR_XEON_D_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
- MSR_XEON_D_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
- MSR_XEON_D_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
- MSR_XEON_D_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
- MSR_XEON_D_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
- MSR_XEON_D_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
- MSR_XEON_D_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
- MSR_XEON_D_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_D_MC5_ADDR 0x00000416\r
-#define MSR_XEON_D_MC6_ADDR 0x0000041A\r
-#define MSR_XEON_D_MC7_ADDR 0x0000041E\r
-#define MSR_XEON_D_MC8_ADDR 0x00000422\r
-#define MSR_XEON_D_MC9_ADDR 0x00000426\r
-#define MSR_XEON_D_MC10_ADDR 0x0000042A\r
-#define MSR_XEON_D_MC11_ADDR 0x0000042E\r
-#define MSR_XEON_D_MC12_ADDR 0x00000432\r
-#define MSR_XEON_D_MC13_ADDR 0x00000436\r
-#define MSR_XEON_D_MC14_ADDR 0x0000043A\r
-#define MSR_XEON_D_MC15_ADDR 0x0000043E\r
-#define MSR_XEON_D_MC16_ADDR 0x00000442\r
-#define MSR_XEON_D_MC17_ADDR 0x00000446\r
-#define MSR_XEON_D_MC18_ADDR 0x0000044A\r
-#define MSR_XEON_D_MC19_ADDR 0x0000044E\r
-#define MSR_XEON_D_MC20_ADDR 0x00000452\r
-#define MSR_XEON_D_MC21_ADDR 0x00000456\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_XEON_D_MCi_MISC\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_MISC);\r
- AsmWriteMsr64 (MSR_XEON_D_MC6_MISC, Msr);\r
- @endcode\r
- @note MSR_XEON_D_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
- MSR_XEON_D_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
- MSR_XEON_D_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
- MSR_XEON_D_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
- MSR_XEON_D_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
- MSR_XEON_D_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
- MSR_XEON_D_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
- MSR_XEON_D_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
- MSR_XEON_D_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
- MSR_XEON_D_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
- MSR_XEON_D_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
- MSR_XEON_D_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
- MSR_XEON_D_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
- MSR_XEON_D_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
- MSR_XEON_D_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
- MSR_XEON_D_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
- MSR_XEON_D_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_D_MC5_MISC 0x00000417\r
-#define MSR_XEON_D_MC6_MISC 0x0000041B\r
-#define MSR_XEON_D_MC7_MISC 0x0000041F\r
-#define MSR_XEON_D_MC8_MISC 0x00000423\r
-#define MSR_XEON_D_MC9_MISC 0x00000427\r
-#define MSR_XEON_D_MC10_MISC 0x0000042B\r
-#define MSR_XEON_D_MC11_MISC 0x0000042F\r
-#define MSR_XEON_D_MC12_MISC 0x00000433\r
-#define MSR_XEON_D_MC13_MISC 0x00000437\r
-#define MSR_XEON_D_MC14_MISC 0x0000043B\r
-#define MSR_XEON_D_MC15_MISC 0x0000043F\r
-#define MSR_XEON_D_MC16_MISC 0x00000443\r
-#define MSR_XEON_D_MC17_MISC 0x00000447\r
-#define MSR_XEON_D_MC18_MISC 0x0000044B\r
-#define MSR_XEON_D_MC19_MISC 0x0000044F\r
-#define MSR_XEON_D_MC20_MISC 0x00000453\r
-#define MSR_XEON_D_MC21_MISC 0x00000457\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_XEON_D_PKG_C8_RESIDENCY (0x00000630)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_D_PKG_C8_RESIDENCY 0x00000630\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_PKG_C8_RESIDENCY\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset\r
- /// that this package is in processor-specific C8 states. Count at the\r
- /// same frequency as the TSC.\r
- ///\r
- UINT32 C8ResidencyCounter:32;\r
- ///\r
- /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C8 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C8ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_XEON_D_PKG_C9_RESIDENCY (0x00000631)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_D_PKG_C9_RESIDENCY 0x00000631\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_PKG_C9_RESIDENCY\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset\r
- /// that this package is in processor-specific C9 states. Count at the\r
- /// same frequency as the TSC.\r
- ///\r
- UINT32 C9ResidencyCounter:32;\r
- ///\r
- /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C9 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C9ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_XEON_D_PKG_C10_RESIDENCY (0x00000632)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_D_PKG_C10_RESIDENCY 0x00000632\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_PKG_C10_RESIDENCY\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C10 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C10ResidencyCounter:32;\r
- ///\r
- /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C10 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C10ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER;\r
-\r
-\r
/**\r
Package. Cache Allocation Technology Configuration (R/W).\r
\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.\r
\r
**/\r
\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
+/**\r
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+ handler to handle unsuccessful read of this MSR.\r
+\r
+ @param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r
+ AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
+**/\r
+#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
+ /// MSR, the configuration of AES instruction set availability is as\r
+ /// follows: 11b: AES instructions are not available until next RESET.\r
+ /// otherwise, AES instructions are available. Note, AES instruction set\r
+ /// is not available if read is unsuccessful. If the configuration is not\r
+ /// 01b, AES instruction can be mis-configured if a privileged agent\r
+ /// unintentionally writes 11b.\r
+ ///\r
+ UINT32 AESConfiguration:2;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r
+ AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
+**/\r
+#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7\r
+\r
+\r
/**\r
Package. Reserved Attempt to read/write will cause #UD.\r
\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.17.\r
\r
**/\r
\r
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r
\r
\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
+**/\r
+#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
/**\r
Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
UINT32 FastStrings:1;\r
UINT32 Reserved1:2;\r
///\r
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W).\r
+ /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r
+ /// is 1.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Precise Event Based Sampling Unavailable (RO).\r
+ /// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r
///\r
UINT32 PEBS:1;\r
UINT32 Reserved4:3;\r
} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r
\r
\r
+/**\r
+ Miscellaneous Feature Control (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L1 data cache prefetcher.\r
+ ///\r
+ UINT32 DCUHardwarePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L2 hardware prefetcher.\r
+ ///\r
+ UINT32 L2HardwarePrefetcherDisable:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
/**\r
Shared. Offcore Response Event Select Register (R/W).\r
\r
#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
\r
\r
-/**\r
- Thread. See Table 35-2.\r
-\r
- @param ECX MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
/**\r
Thread. See Table 35-2.\r
\r
#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
\r
\r
-/**\r
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC3_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC3_CTL 0x0000040C\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_XEON_PHI_MC3_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC3_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC3_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC3_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC4_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC4_CTL 0x00000410\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_XEON_PHI_MC4_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC4_STATUS 0x00000411\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register\r
- is either not implemented or contains no address if the ADDRV flag in the\r
- MSR_MC4_STATUS register is clear. When not implemented in the processor, all\r
- reads and writes to this MSR will cause a general-protection exception.\r
-\r
- @param ECX MSR_XEON_PHI_MC4_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC4_ADDR 0x00000412\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC5_CTL (0x00000414)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC5_CTL 0x00000414\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_XEON_PHI_MC5_STATUS (0x00000415)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC5_STATUS 0x00000415\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC5_ADDR (0x00000416)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC5_ADDR 0x00000416\r
-\r
-\r
/**\r
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
\r
\r
\r
/**\r
- Package. Base TDP Ratio (R/O) See Table 35-20.\r
+ Package. Base TDP Ratio (R/O) See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-20.\r
+ Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-20.\r
+ Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. ConfigTDP Control (R/W) See Table 35-20.\r
+ Package. ConfigTDP Control (R/W) See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. ConfigTDP Control (R/W) See Table 35-20.\r
+ Package. ConfigTDP Control (R/W) See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)\r
@param EAX Lower 32-bits of MSR value.\r
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