REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: cbduggap <chinni.b.duggapu@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
global ASM_PFX(LoadMicrocodeDefault)\r
ASM_PFX(LoadMicrocodeDefault):\r
; Inputs:\r
global ASM_PFX(LoadMicrocodeDefault)\r
ASM_PFX(LoadMicrocodeDefault):\r
; Inputs:\r
- ; rsp -> LoadMicrocodeParams pointer\r
+ ; rcx -> LoadMicrocodeParams pointer\r
; Register Usage:\r
; rsp Preserved\r
; All others destroyed\r
; Register Usage:\r
; rsp Preserved\r
; All others destroyed\r
\r
cmp rsp, 0\r
jz ParamError\r
\r
cmp rsp, 0\r
jz ParamError\r
- mov eax, dword [rsp + 8] ; Parameter pointer\r
- cmp eax, 0\r
\r
; skip loading Microcode if the MicrocodeCodeSize is zero\r
; and report error if size is less than 2k\r
\r
; skip loading Microcode if the MicrocodeCodeSize is zero\r
; and report error if size is less than 2k\r
jne ParamError\r
\r
; UPD structure is compliant with FSP spec 2.4\r
jne ParamError\r
\r
; UPD structure is compliant with FSP spec 2.4\r
- mov eax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
- cmp eax, 0\r
+ mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
+ cmp rax, 0\r
- mov esi, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
- cmp esi, 0\r
+ mov rsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
+ cmp rsi, 0\r
jnz CheckMainHeader\r
\r
ParamError:\r
jnz CheckMainHeader\r
\r
ParamError:\r
; UPD structure is compliant with FSP spec 2.4\r
; Is automatic size detection ?\r
mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
; UPD structure is compliant with FSP spec 2.4\r
; Is automatic size detection ?\r
mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
- cmp rax, 0ffffffffffffffffh\r
+ mov rcx, 0ffffffffffffffffh\r
+ cmp rax, rcx\r
jz LoadMicrocodeDefault4\r
\r
; Address >= microcode region address + microcode region size?\r
jz LoadMicrocodeDefault4\r
\r
; Address >= microcode region address + microcode region size?\r
;\r
; Save parameter pointer in rdx\r
;\r
;\r
; Save parameter pointer in rdx\r
;\r
- mov rdx, qword [rsp + 8]\r
-\r
;\r
; Enable FSP STACK\r
;\r
;\r
; Enable FSP STACK\r
;\r
;\r
ENABLE_SSE\r
ENABLE_AVX\r
;\r
ENABLE_SSE\r
ENABLE_AVX\r
+ ;\r
+ ; Save Input Parameter in YMM10\r
+ ;\r
+ SAVE_RCX\r
;\r
; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6\r
;\r
;\r
; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6\r
;\r
;\r
; Check Parameter\r
;\r
;\r
; Check Parameter\r
;\r
- mov rax, qword [rsp + 8]\r
- cmp rax, 0\r
- mov rax, 08000000000000002h\r
+ cmp rcx, 0\r
+ mov rcx, 08000000000000002h\r
jz TempRamInitExit\r
\r
;\r
jz TempRamInitExit\r
\r
;\r
jnz TempRamInitExit\r
\r
; Load microcode\r
jnz TempRamInitExit\r
\r
; Load microcode\r
CALL_YMM ASM_PFX(LoadMicrocodeDefault)\r
SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 in YMM9 (upper 128bits).\r
; @note If return value rax is not 0, microcode did not load, but continue and attempt to boot.\r
\r
; Call Sec CAR Init\r
CALL_YMM ASM_PFX(LoadMicrocodeDefault)\r
SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 in YMM9 (upper 128bits).\r
; @note If return value rax is not 0, microcode did not load, but continue and attempt to boot.\r
\r
; Call Sec CAR Init\r
CALL_YMM ASM_PFX(SecCarInit)\r
cmp rax, 0\r
jnz TempRamInitExit\r
\r
CALL_YMM ASM_PFX(SecCarInit)\r
cmp rax, 0\r
jnz TempRamInitExit\r
\r
CALL_YMM ASM_PFX(EstablishStackFsp)\r
cmp rax, 0\r
jnz TempRamInitExit\r
CALL_YMM ASM_PFX(EstablishStackFsp)\r
cmp rax, 0\r
jnz TempRamInitExit\r
LXMMN xmm5, %1, 1\r
%endmacro\r
\r
LXMMN xmm5, %1, 1\r
%endmacro\r
\r
+;\r
+; Upper half of YMM10 to save/restore RCX\r
+;\r
+;\r
+; Save RCX to YMM10[128:191]\r
+; Modified: XMM5 and YMM10\r
+;\r
+\r
+%macro SAVE_RCX 0\r
+ LYMMN ymm10, xmm5, 1\r
+ SXMMN xmm5, 0, rcx\r
+ SYMMN ymm10, 1, xmm5\r
+ %endmacro\r
+\r
+;\r
+; Restore RCX from YMM10[128:191]\r
+; Modified: XMM5 and RCX\r
+;\r
+\r
+%macro LOAD_RCX 0\r
+ LYMMN ymm10, xmm5, 1\r
+ movq rcx, xmm5\r
+ %endmacro\r
+\r
;\r
; YMM7[128:191] for calling stack\r
; arg 1:Entry\r
;\r
; YMM7[128:191] for calling stack\r
; arg 1:Entry\r
; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
; whether the processor supports SSE instruction.\r
;\r
; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
; whether the processor supports SSE instruction.\r
;\r
mov rax, 1\r
cpuid\r
bt rdx, 25\r
mov rax, 1\r
cpuid\r
bt rdx, 25\r
;\r
bt ecx, 19\r
jnc SseError\r
;\r
bt ecx, 19\r
jnc SseError\r
\r
;\r
; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
\r
;\r
; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
%endmacro\r
\r
%macro ENABLE_AVX 0\r
%endmacro\r
\r
%macro ENABLE_AVX 0\r
mov eax, 1\r
cpuid\r
and ecx, 10000000h\r
mov eax, 1\r
cpuid\r
and ecx, 10000000h\r
xgetbv ; result in edx:eax\r
or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable SSE state and AVX state\r
xsetbv\r
xgetbv ; result in edx:eax\r
or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable SSE state and AVX state\r
xsetbv\r