+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Library/ArmCpuLib.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)\r
-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)\r
-\r
-// VOID\r
-// ArmCpuSynchronizeWait (\r
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
-// );\r
-ASM_PFX(ArmCpuSynchronizeWait):\r
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
- bx lr\r
- b ASM_PFX(CArmCpuSynchronizeWait)\r
-\r
-\r
-#if 0\r
-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)\r
-GCC_ASM_EXPORT(ArmGetScuBaseAddress)\r
-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)\r
-\r
-// VOID\r
-// ArmCpuSynchronizeWait (\r
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
-// );\r
-ASM_PFX(ArmCpuSynchronizeWait):\r
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
- beq ArmWaitScuEnabled\r
- b ASM_PFX(CArmCpuSynchronizeWait)\r
-\r
-// IN None\r
-// OUT r0 = SCU Base Address\r
-ASM_PFX(ArmGetScuBaseAddress):\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
-\r
-ASM_PFX(ArmWaitScuEnabled):\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- add r0, r0, #A9_SCU_CONTROL_OFFSET\r
- ldr r0, [r0]\r
- cmp r0, #1\r
- bne ArmWaitScuEnabled\r
- bx lr\r
-#endif\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Library/ArmCpuLib.h>\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
- EXPORT ArmCpuSynchronizeWait\r
- EXPORT ArmGetScuBaseAddress\r
- IMPORT CArmCpuSynchronizeWait\r
-\r
- PRESERVE8\r
- AREA ArmCortexA9Helper, CODE, READONLY\r
-\r
-// VOID\r
-// ArmCpuSynchronizeWait (\r
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
-// );\r
-ArmCpuSynchronizeWait\r
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
- beq ArmWaitScuEnabled\r
- b CArmCpuSynchronizeWait\r
-\r
-// IN None\r
-// OUT r0 = SCU Base Address\r
-ArmGetScuBaseAddress\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
-\r
-ArmWaitScuEnabled\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- add r0, r0, #A9_SCU_CONTROL_OFFSET\r
- ldr r0, [r0]\r
- cmp r0, #1\r
- bne ArmWaitScuEnabled\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/ArmCpuLib.h>\r
-#include <Library/ArmGicLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Chipset/ArmV7.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)\r
-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)\r
-// Dirty hack to get the Fixed value of GicDistributorBase\r
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdGicDistributorBase)\r
-\r
-\r
-// VOID\r
-// ArmCpuSynchronizeWait (\r
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
-// );\r
-ASM_PFX(ArmCpuSynchronizeWait):\r
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
- beq ArmWaitGicDistributorEnabled\r
- push {r1,lr}\r
- LoadConstantToReg (ASM_PFX(CArmCpuSynchronizeWait), r1)\r
- blx r1\r
- pop {r1,lr}\r
- bx lr\r
-\r
-// IN None\r
-ArmWaitGicDistributorEnabled:\r
- LoadConstantToReg (ASM_PFX(_gPcd_FixedAtBuild_PcdGicDistributorBase), r0)\r
- ldr r0, [r0]\r
-_WaitGicDistributor:\r
- ldr r1, [r0, #ARM_GIC_ICDDCR]\r
- cmp r1, #1\r
- bne _WaitGicDistributor\r
- bx lr\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/ArmCpuLib.h>\r
-#include <Library/ArmGicLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Chipset/ArmV7.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmCpuSynchronizeWait\r
- IMPORT CArmCpuSynchronizeWait\r
- // Dirty hack to get the Fixed value of GicDistributorBase\r
- IMPORT _gPcd_FixedAtBuild_PcdGicDistributorBase\r
-\r
- PRESERVE8\r
- AREA ArmCortexA15Helper, CODE, READONLY\r
-\r
-// VOID\r
-// ArmCpuSynchronizeWait (\r
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
-// );\r
-ArmCpuSynchronizeWait\r
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
- beq ArmWaitGicDistributorEnabled\r
- // Case when the stack has been set up\r
- push {r1,lr}\r
- LoadConstantToReg (CArmCpuSynchronizeWait, r1)\r
- blx r1\r
- pop {r1,lr}\r
- bx lr\r
-\r
-\r
-// IN None\r
-ArmWaitGicDistributorEnabled\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)\r
- ldr r0, [r0]\r
-_WaitGicDistributor\r
- ldr r1, [r0, #ARM_GIC_ICDDCR]\r
- cmp r1, #1\r
- bne _WaitGicDistributor\r
- bx lr\r
-\r
- END\r
projects / mirror_edk2.git / commitdiff