PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);\r
\r
//\r
- // The host to pci bridge, the host memory and io addresses are\r
- // direct mapped to pci addresses, so no need translate, set bases to 0.\r
+ // The host to PCI bridge. The host memory addresses are direct mapped to PCI\r
+ // addresses, so there's no need to translate them. IO addresses need\r
+ // translation however.\r
//\r
- PrivateData->MemBase = ResAperture->MemBase;\r
- PrivateData->IoBase = ResAperture->IoBase;\r
+ PrivateData->MemBase = ResAperture->MemBase;\r
+ PrivateData->IoBase = ResAperture->IoBase;\r
+ PrivateData->IoTranslation = ResAperture->IoTranslation;\r
\r
//\r
// The host bridge only supports 32bit addressing for memory\r
)\r
{\r
EFI_STATUS Status;\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
UINT8 InStride;\r
UINT8 OutStride;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
return Status;\r
}\r
\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+ //\r
+ // The addition below is performed in UINT64 modular arithmetic, in\r
+ // accordance with the definition of PcdPciIoTranslation in\r
+ // "ArmPlatformPkg.dec". Meaning, the addition below may in fact *decrease*\r
+ // Address, implementing a negative offset translation.\r
+ //\r
+ Address += PrivateData->IoTranslation;\r
+\r
InStride = mInStride[Width];\r
OutStride = mOutStride[Width];\r
OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r