IntelFsp2Pkg: FSP can utilize bootloader stack

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1485

Current FSP utilizes pre-allocated temporary memory from
boot loader for both heap and stack. To reduce overall
temporary memory usage FSP may share the same stack with
boot loader and only needs a smaller memory for heap,
no separate memory required for stack.
Setting PcdFspHeapSizePercentage to 0 to enable FSP sharing
stack with boot loader, in this case boot loader stack
has to be large enough for FSP to use. Default is 50
(half memory heap and half memory stack) for backward
compatible with original model.

Test: Verified on internal platform and booting successfully
      with both modes.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index dafe6f599304d2e2674cccce71be122bef0df048..0024254e0ef0c7d1d58f96b143d818c63d2100d3 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -1,7 +1,7 @@
 ## @file\r
 #  Sec Core for FSP\r
 #\r
 ## @file\r
 #  Sec Core for FSP\r
 #\r

-#  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+#  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r

 #\r
 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #\r
 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r


@@ -38,6 +38,7 @@
   Ia32/FspApiEntryM.nasm\r
   Ia32/FspApiEntryCommon.nasm\r
   Ia32/FspHelper.nasm\r
   Ia32/FspApiEntryM.nasm\r
   Ia32/FspApiEntryCommon.nasm\r
   Ia32/FspHelper.nasm\r

+  Ia32/ReadEsp.nasm\r

 \r
 [Binaries.Ia32]\r
   RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC\r
 \r
 [Binaries.Ia32]\r
   RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC\r

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 9c9a84db0a3e1aa4a9663d587739b6d1a8d0455d..916ad4ff0d7b32a0e0d77920c79c438b4d8857f4 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -1,7 +1,7 @@
 ;; @file\r
 ;  Provide FSP API entry points.\r
 ;\r
 ;; @file\r
 ;  Provide FSP API entry points.\r
 ;\r

-; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r

 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r


@@ -19,6 +19,7 @@
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))\r
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))\r
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))\r
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))\r
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))\r
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))\r

+extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))\r

 \r
 struc FSPM_UPD_COMMON\r
     ; FSP_UPD_HEADER {\r
 \r
 struc FSPM_UPD_COMMON\r
     ; FSP_UPD_HEADER {\r


@@ -128,15 +129,55 @@ ASM_PFX(FspApiCommonContinue):
   add    edx, [eax + FSP_HEADER_CFGREG_OFFSET]\r
   pop    eax\r
 \r
   add    edx, [eax + FSP_HEADER_CFGREG_OFFSET]\r
   pop    eax\r
 \r

-  FspStackSetup:\r
+FspStackSetup:\r
+  ;\r
+  ; StackBase = temp memory base, StackSize = temp memory size\r
+  ;\r

   mov    edi, [edx + FSPM_UPD_COMMON.StackBase]\r
   mov    ecx, [edx + FSPM_UPD_COMMON.StackSize]\r
   mov    edi, [edx + FSPM_UPD_COMMON.StackBase]\r
   mov    ecx, [edx + FSPM_UPD_COMMON.StackSize]\r

+\r
+  ;\r
+  ; Keep using bootloader stack if heap size % is 0\r
+  ;\r
+  mov    bl, BYTE [ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))]\r
+  cmp    bl, 0\r
+  jz     SkipStackSwitch\r
+\r
+  ;\r
+  ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't equal 0\r
+  ;\r

   add    edi, ecx\r
   ;\r
   add    edi, ecx\r
   ;\r

-  ; Setup new FSP stack\r
+  ; Switch to new FSP stack\r

   ;\r
   ;\r

-  xchg    edi, esp                                ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size\r
-  mov     ebx, esp                                ; Put Stack base + Stack size in ebx\r
+  xchg   edi, esp                                ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size\r
+\r
+SkipStackSwitch:\r
+  ;\r
+  ; If heap size % is 0:\r
+  ;   EDI is FSPM_UPD_COMMON.StackBase and will hold ESP later (boot loader stack pointer)\r
+  ;   ECX is FSPM_UPD_COMMON.StackSize\r
+  ;   ESP is boot loader stack pointer (no stack switch)\r
+  ;   BL  is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON.StackBase later)\r
+  ;\r
+  ; If heap size % is not 0\r
+  ;   EDI is boot loader stack pointer\r
+  ;   ECX is FSPM_UPD_COMMON.StackSize\r
+  ;   ESP is new stack (FSPM_UPD_COMMON.StackBase + FSPM_UPD_COMMON.StackSize)\r
+  ;   BL  is NOT 0 to indicate stack has switched\r
+  ;\r
+  cmp    bl, 0\r
+  jnz    StackHasBeenSwitched\r
+\r
+  mov    ebx, edi                                ; Put FSPM_UPD_COMMON.StackBase to ebx as temp memory base\r
+  mov    edi, esp                                ; Put boot loader stack pointer to edi\r
+  jmp    StackSetupDone\r
+\r
+StackHasBeenSwitched:\r
+  mov    ebx, esp                                ; Put Stack base + Stack size in ebx\r
+  sub    ebx, ecx                                ; Stack base + Stack size - Stack size as temp memory base\r
+\r
+StackSetupDone:\r

 \r
   ;\r
   ; Pass the API Idx to SecStartup\r
 \r
   ;\r
   ; Pass the API Idx to SecStartup\r


@@ -170,7 +211,6 @@ ASM_PFX(FspApiCommonContinue):
   ;\r
   ; Pass stack base and size into the PEI Core\r
   ;\r
   ;\r
   ; Pass stack base and size into the PEI Core\r
   ;\r

-  sub     ebx, ecx            ; Stack base + Stack size - Stack size\r

   push    ebx\r
   push    ecx\r
 \r
   push    ebx\r
   push    ecx\r
 \r

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm
new file mode 100644 (file)
index 0000000..ca29f05
--- /dev/null
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm
@@ -0,0 +1,28 @@
+;; @file\r
+;  Provide read ESP function\r
+;\r
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;;\r
+;------------------------------------------------------------------------------\r
+\r
+    SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT32\r
+; EFIAPI\r
+; AsmReadEsp (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmReadEsp)\r
+ASM_PFX(AsmReadEsp):\r
+    mov     eax, esp\r
+    ret\r
+\r

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/SecMain.c
index 70460a3c8befc298546949be0ddab4d05349cd0b..c7caa3e7f927d23fb0284eaad0c2c6a501d30e75 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -1,6 +1,6 @@
 /** @file\r
 \r
 /** @file\r
 \r

-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -83,7 +83,29 @@ SecStartup (
   //\r
   InitializeFloatingPointUnits ();\r
 \r
   //\r
   InitializeFloatingPointUnits ();\r
 \r

+  //\r
+  // Scenario 1 memory map when running on bootloader stack\r
+  //\r
+  // |-------------------|---->\r
+  // |Idt Table          |\r
+  // |-------------------|\r
+  // |PeiService Pointer |\r
+  // |-------------------|\r
+  // |                   |\r
+  // |                   |\r
+  // |      Heap         |\r
+  // |                   |\r
+  // |                   |\r
+  // |-------------------|---->  TempRamBase\r
+  //\r
+  //\r
+  // |-------------------|\r
+  // |Bootloader stack   |----> somewhere in memory, FSP will share this stack.\r
+  // |-------------------|\r

 \r
 \r

+  //\r
+  // Scenario 2 memory map when running FSP on a separate stack\r
+  //\r

   // |-------------------|---->\r
   // |Idt Table          |\r
   // |-------------------|\r
   // |-------------------|---->\r
   // |Idt Table          |\r
   // |-------------------|\r


@@ -135,11 +157,19 @@ SecStartup (
   SecCoreData.BootFirmwareVolumeSize = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength;\r
 \r
   SecCoreData.TemporaryRamBase       = (VOID*)(UINTN) TempRamBase;\r
   SecCoreData.BootFirmwareVolumeSize = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength;\r
 \r
   SecCoreData.TemporaryRamBase       = (VOID*)(UINTN) TempRamBase;\r

-  SecCoreData.TemporaryRamSize       = SizeOfRam;\r
-  SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
-  SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;\r
-  SecCoreData.StackBase              = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r
-  SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+  if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {\r
+    SecCoreData.TemporaryRamSize       = SizeOfRam; // stack size that is going to be copied to the permanent memory\r
+    SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
+    SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize;\r
+    SecCoreData.StackBase              = (VOID *)GetFspEntryStack(); // Share the same boot loader stack\r
+    SecCoreData.StackSize              = 0;\r
+  } else {\r
+    SecCoreData.TemporaryRamSize       = SizeOfRam;\r
+    SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
+    SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;\r
+    SecCoreData.StackBase              = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r
+    SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+  }\r

 \r
   DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));\r
   DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize));\r
 \r
   DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));\r
   DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize));\r


@@ -194,15 +224,37 @@ SecTemporaryRamSupport (
   UINTN             HeapSize;\r
   UINTN             StackSize;\r
 \r
   UINTN             HeapSize;\r
   UINTN             StackSize;\r
 \r

-  HeapSize   = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ;\r
-  StackSize  = CopySize - HeapSize;\r
+  UINTN             CurrentStack;\r
+  UINTN             FspStackBase;\r
+\r
+  if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {\r
+\r
+    CurrentStack = AsmReadEsp();\r
+    FspStackBase = (UINTN)GetFspEntryStack();\r

 \r
 \r

-  OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
-  NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize);\r
+    StackSize = FspStackBase - CurrentStack;\r
+    HeapSize  = CopySize;\r

 \r
 \r

-  OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);\r
-  NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r
+    OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
+    NewHeap = (VOID*)((UINTN)PermanentMemoryBase);\r

 \r
 \r

+    OldStack = (VOID*)CurrentStack;\r
+    //\r
+    //The old stack is copied at the end of the stack region because stack grows down.\r
+    //\r
+    NewStack = (VOID*)((UINTN)PermanentMemoryBase - StackSize);\r
+\r
+  } else {\r
+    HeapSize   = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ;\r
+    StackSize  = CopySize - HeapSize;\r
+\r
+    OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
+    NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize);\r
+\r
+    OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);\r
+    NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r
+\r
+  }\r

   //\r
   // Migrate Heap\r
   //\r
   //\r
   // Migrate Heap\r
   //\r

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h b/IntelFsp2Pkg/FspSecCore/SecMain.h
index 19ac2fbfc168147f027e13c7ee57a6fecd69a5ec..d8fc00b714573e6d209397179589471be2c236d1 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/SecMain.h
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.h
@@ -135,4 +135,17 @@ ProcessLibraryConstructorList (
   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r

+/**\r
+\r
+  Return value of esp.\r
+\r
+  @return  value of esp.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmReadEsp (\r
+  VOID\r
+  );\r
+\r

 #endif\r
 #endif\r

diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index 64a31b350539a15dadff87da96e17a66bef9bae8..d4c6d221a14ad6c8ebc815d018668d03f3f4b313 100644 (file)
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -86,8 +86,12 @@
   gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003\r
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion     |      0x20| UINT8|0x00000002\r
 \r
   gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003\r
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion     |      0x20| UINT8|0x00000002\r
 \r

+  #\r

   # x % of FSP temporary memory will be used for heap\r
   # (100 - x) % of FSP temporary memory will be used for stack\r
   # x % of FSP temporary memory will be used for heap\r
   # (100 - x) % of FSP temporary memory will be used for stack\r

+  # 0 means FSP will share the stack with boot loader and FSP temporary memory is heap\r
+  #   Note: This mode assumes boot loader stack is large enough for FSP to use.\r
+  #\r

   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage    |        50| UINT8|0x10000004\r
   #\r
   # Maximal Interrupt supported in IDT table.\r
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage    |        50| UINT8|0x10000004\r
   #\r
   # Maximal Interrupt supported in IDT table.\r