CpuPageTableLib: Refactor the logic

The patch replaces
  LinearAddress + Offset == RegionStart
with
  ((LinearAddress + Offset) & RegionMask) == 0

The replace should not cause any behavior change.

Because:
1. In first loop of while when LinearAddress + Offset == RegionStart,
  because the lower "BitStart" bits of RegionStart are all-zero,
  all lower "BitStart" bits of (LinearAddress + Offset) are all-zero.
  Because all lower "BitStart" bits of RegionMask is all-one and
  bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0.

2. In following loops of the while, even RegionStart is increased
  by RegionLength, the lower "BitStart" bits are still all-zero.
  So the two expressions still semantically equal to each other.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index e23158c17eaac50068697fa3af7daaf5aea89afe..5f751048a32b3469904ba892bb4d9c7d2e0dbb4f 100644 (file)
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -360,7 +360,7 @@ PageTableLibMapInLevel (
   PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);\r
   while (Offset < Length && Index < 512) {\r
     SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));\r
-    if ((Level <= MaxLeafLevel) && (LinearAddress + Offset == RegionStart) && (SubLength == RegionLength)) {\r
+    if ((Level <= MaxLeafLevel) && (((LinearAddress + Offset) & RegionMask) == 0) && (SubLength == RegionLength)) {\r
       //\r
       // Create one entry mapping the entire region (1G, 2M or 4K).\r
       //\r