ArmPkg: remove unused ArmGicSecLib library implementation

This module is not used anywhere under edk2 or edk2-platforms, so let's
remove it. This removes the only dependency on ArmPlatformLib from ArmPkg.
While at it, remove a mention of ArmPlatformPkg from a comment in the
.dec file as well.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index f99054a7de3e51410bbc63f7aba5fff1d75f3bbb..f3fb77c16f75cbd02cf8b961a387f7f1c4fb75a2 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -224,8 +224,8 @@
 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
 \r
   # System Memory (DRAM): These PCDs define the region of in-built system memory\r
-  # Some platforms can get DRAM extensions, these additional regions will be declared\r
-  # to UEFI by ArmPlatformLib\r
+  # Some platforms can get DRAM extensions, these additional regions may be\r
+  # declared to UEFI using separate resource descriptor HOBs\r
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
 \r

diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
index a396c96bf83b18078305156791f2e69b3c51c88a..622720ab2aefa0a3d2f824af86e96a1fd1ab3946 100644 (file)
--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -121,7 +121,6 @@
   ArmPkg/Drivers/CpuPei/CpuPei.inf\r
   ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
   ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
-  ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
   ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf\r
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
 \r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
deleted file mode 100644 (file)
index fc2e1bc..0000000
--- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+++ /dev/null
@@ -1,52 +0,0 @@
-#/* @file\r
-#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
-#\r
-#  This program and the accompanying materials\r
-#  are licensed and made available under the terms and conditions of the BSD License\r
-#  which accompanies this distribution.  The full text of the license may be found at\r
-#  http://opensource.org/licenses/bsd-license.php\r
-#\r
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
-  INF_VERSION                    = 0x00010005\r
-  BASE_NAME                      = ArmGicSecLib\r
-  FILE_GUID                      = 85f3cf80-b5f4-11df-9855-0002a5d5c51b\r
-  MODULE_TYPE                    = SEC\r
-  VERSION_STRING                 = 1.0\r
-  LIBRARY_CLASS                  = ArmGicLib\r
-\r
-[Sources]\r
-  ArmGicLib.c\r
-  ArmGicSecLib.c\r
-\r
-  GicV2/ArmGicV2Lib.c\r
-  GicV2/ArmGicV2SecLib.c\r
-\r
-[Sources.ARM]\r
-  GicV3/Arm/ArmGicV3.S     | GCC\r
-  GicV3/Arm/ArmGicV3.asm   | RVCT\r
-\r
-[Sources.AARCH64]\r
-  GicV3/AArch64/ArmGicV3.S\r
-\r
-[Packages]\r
-  ArmPkg/ArmPkg.dec\r
-  ArmPlatformPkg/ArmPlatformPkg.dec\r
-  MdePkg/MdePkg.dec\r
-  MdeModulePkg/MdeModulePkg.dec\r
-\r
-[LibraryClasses]\r
-  ArmLib\r
-  DebugLib\r
-  IoLib\r
-  ArmGicArchLib\r
-\r
-[Pcd]\r
-  gArmPlatformTokenSpaceGuid.PcdCoreCount\r
-\r
-[FeaturePcd]\r
-  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy\r

diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c
deleted file mode 100644 (file)
index ac1e0e4..0000000
--- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/** @file\r
-*\r
-*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-*\r
-*  This program and the accompanying materials\r
-*  are licensed and made available under the terms and conditions of the BSD License\r
-*  which accompanies this distribution.  The full text of the license may be found at\r
-*  http://opensource.org/licenses/bsd-license.php\r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmGicLib.h>\r
-\r
-/*\r
- * This function configures the all interrupts to be Non-secure.\r
- *\r
- */\r
-VOID\r
-EFIAPI\r
-ArmGicV2SetupNonSecure (\r
-  IN  UINTN         MpId,\r
-  IN  INTN          GicDistributorBase,\r
-  IN  INTN          GicInterruptInterfaceBase\r
-  )\r
-{\r
-  UINTN InterruptId;\r
-  UINTN CachedPriorityMask;\r
-  UINTN Index;\r
-  UINTN MaxInterrupts;\r
-\r
-  CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
-\r
-  // Set priority Mask so that no interrupts get through to CPU\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
-\r
-  InterruptId   = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
-  MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);\r
-\r
-  // Only try to clear valid interrupts. Ignore spurious interrupts.\r
-  while ((InterruptId & 0x3FF) < MaxInterrupts) {\r
-    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
-    ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);\r
-\r
-    // Next\r
-    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
-  }\r
-\r
-  // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
-  if (ArmPlatformIsPrimaryCore (MpId)) {\r
-    // Ensure all GIC interrupts are Non-Secure\r
-    for (Index = 0; Index < (MaxInterrupts / 32); Index++) {\r
-      MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
-    }\r
-  } else {\r
-    // The secondary cores only set the Non Secure bit to their banked PPIs\r
-    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
-  }\r
-\r
-  // Ensure all interrupts can get through the priority mask\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicV2EnableInterruptInterface (\r
-  IN  INTN          GicInterruptInterfaceBase\r
-  )\r
-{\r
-  // Set Priority Mask to allow interrupts\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
-\r
-  // Enable CPU interface in Secure world\r
-  // Enable CPU interface in Non-secure World\r
-  // Signal Secure Interrupts to CPU using FIQ line *\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
-      ARM_GIC_ICCICR_ENABLE_SECURE |\r
-      ARM_GIC_ICCICR_ENABLE_NS |\r
-      ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicV2DisableInterruptInterface (\r
-  IN  INTN          GicInterruptInterfaceBase\r
-  )\r
-{\r
-  UINT32    ControlValue;\r
-\r
-  // Disable CPU interface in Secure world and Non-secure World\r
-  ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
-  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
-}\r