</Arch>\r
<Arch ArchType="IPF">\r
<Filename>Math64.c</Filename>\r
+ <Filename>Ipf/PalCallStatic.s</Filename>\r
<Filename>Ipf/setjmp.s</Filename>\r
<Filename>Ipf/SwitchStack.s</Filename>\r
<Filename>Ipf/Unaligned.c</Filename>\r
call @Base ; push eip\r
@Base:\r
pop bp ; ebp <- offset @Base\r
+ DB 67h ; address size override\r
+ push [esp + sizeof (IA32_REGS) + 2]\r
+ lea eax, [esi + (offset @RealMode - offset @Base)]\r
+ push eax\r
+ retf\r
+@RealMode:\r
mov cs:[esi + (offset SavedSs - offset @Base)], edx\r
mov cs:[esi + (offset SavedEsp - offset @Base)], bx\r
DB 66h\r
push 10h\r
pop ecx ; ecx <- selector for data segments\r
lgdt fword ptr [edx + (offset _16Gdtr - offset SavedCr0)]\r
+ pushfd\r
call fword ptr [edx + (offset _EntryPoint - offset SavedCr0)]\r
+ popfd\r
lidt fword ptr [esp + 36] ; restore protected mode IDTR\r
lea eax, [ebp - sizeof (IA32_REGS)]\r
ret\r
.auto\r
.text\r
\r
+.global PalCallStatic\r
+.type PalCallStatic, @function\r
+\r
.proc CpuFlushTlb\r
.type CpuFlushTlb, @function\r
CpuFlushTlb::\r
- mov r8 = ip\r
- mov r9 = -1\r
- dep.z r10 = -1, 61, 3\r
- and r8 = r8, r10\r
- ptc.l r8, r9\r
+ alloc loc0 = ar.pfs, 0, 2, 5, 0\r
+ mov out0 = 0\r
+ mov out1 = 6\r
+ mov out2 = 0\r
+ mov out3 = 0\r
+ mov out4 = 0\r
+ mov loc1 = b0\r
+ br.call.sptk b0 = PalCallStatic\r
+ rsm 1 << 14 // Disable interrupts\r
+ mov ar.pfs = loc0\r
+ extr.u r14 = r10, 32, 32 // r14 <- count1\r
+ extr.u r15 = r11, 32, 32 // r15 <- stride1\r
+ extr.u r10 = r10, 0, 32 // r10 <- count2\r
+ mov loc0 = psr\r
+ extr.u r11 = r11, 0, 32 // r11 <- stride2\r
+ br.cond.sptk LoopPredicate\r
+LoopOuter:\r
+ mov ar.lc = r10 // LC <- count2\r
+ mov ar.ec = r0 // EC <- 0\r
+Loop:\r
+ ptc.e r9\r
+ add r9 = r11, r9 // r9 += stride2\r
+ br.ctop.sptk Loop\r
+ add r9 = r15, r9 // r9 += stride1\r
+LoopPredicate:\r
+ cmp.ne p6, p7 = r0, r14 // count1 == 0?\r
+ add r14 = -1, r14\r
+(p6) br.cond.sptk LoopOuter\r
+ mov psr.l = loc0\r
+ mov b0 = loc1\r
br.ret.sptk.many b0\r
.endp\r
--- /dev/null
+/// @file\r
+/// Contains an implementation of CallPalProcStatic on Itanium-based\r
+/// architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution. The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: PalCallStatic.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc PalCallStatic\r
+.type PalCallStatic, @function\r
+.regstk 5, 0, 0, 0\r
+PalCallStatic::\r
+ cmp.ne p6, p7 = r0, in0\r
+ mov r31 = in4\r
+ mov r8 = ip\r
+(p6) mov in0 = ar.k5\r
+ add r8 = (PalProcReturn - PalCallStatic), r8\r
+ mov in4 = b0\r
+ mov r30 = in3\r
+ mov r29 = in2\r
+ mov b7 = in0\r
+ mov in3 = psr\r
+ rsm 1 << 14 // Disable interrupts\r
+ mov r28 = in1\r
+ mov in0 = 256\r
+ mov b0 = r8\r
+ br.cond.sptk b7\r
+PalProcReturn:\r
+ mov psr.l = in3\r
+ cmp.eq p6, p7 = in0, in1 // in1 == PAL_COPY_PAL?\r
+(p6) cmp.eq p6, p7 = r0, r8 // Status == Success?\r
+(p6) mov ar.k5 = in2\r
+ mov b0 = in4\r
+ br.ret.sptk.many b0\r
+.endp PalCallStatic\r
call @Base ; push eip\r
@Base:\r
pop bp ; ebp <- offset @Base\r
+ push [esp + sizeof (IA32_REGS) + 2]\r
+ lea eax, [rsi + (offset @RealMode - offset @Base)]\r
+ push rax\r
+ retf\r
+@RealMode:\r
DB 2eh ; cs:\r
mov [rsi + (offset SavedSs - offset @Base)], edi\r
DB 2eh ; cs:\r
push 10h\r
pop rdx ; rdx <- selector for data segments\r
lgdt fword ptr [rcx + (offset _16Gdtr - offset SavedCr4)]\r
+ pushfq\r
call fword ptr [rcx + (offset _EntryPoint - offset SavedCr4)]\r
+ popfq\r
lidt fword ptr [rsp + 38h] ; restore protected mode IDTR\r
lea eax, [rbp - sizeof (IA32_REGS)]\r
pop gs\r
ASSERT (ExtraStackSize != NULL);\r
\r
*RealModeBufferSize = m16Size;\r
+\r
+ //\r
+ // Extra 4 bytes for return address, and another 4 bytes for mode transition\r
+ //\r
*ExtraStackSize = sizeof (IA32_DWORD_REGS) + 8;\r
}\r
\r