UefiCpuPkg: Add SecCore module

Add SecCore module that uses the PlatformSecLib class for platform
specific actions.  The SecCore module also uses a new PCD to
configure the size of the stack used in the SEC phase.  If the
stack size PCD is set to 0, the stack is configured to use half
of the available temporary RAM.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18636 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/SecCore/FindPeiCore.c b/UefiCpuPkg/SecCore/FindPeiCore.c
new file mode 100644 (file)
index 0000000..60ccaa9
--- /dev/null
+++ b/UefiCpuPkg/SecCore/FindPeiCore.c
@@ -0,0 +1,198 @@
+/** @file\r
+  Locate the entry point for the PEI Core\r
+\r
+  Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+\r
+#include "SecMain.h"\r
+\r
+/**\r
+  Find core image base.\r
+\r
+  @param   BootFirmwareVolumePtr    Point to the boot firmware volume.\r
+  @param   SecCoreImageBase         The base address of the SEC core image.\r
+  @param   PeiCoreImageBase         The base address of the PEI core image.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FindImageBase (\r
+  IN  EFI_FIRMWARE_VOLUME_HEADER       *BootFirmwareVolumePtr,\r
+  OUT EFI_PHYSICAL_ADDRESS             *SecCoreImageBase,\r
+  OUT EFI_PHYSICAL_ADDRESS             *PeiCoreImageBase\r
+  )\r
+{\r
+  EFI_PHYSICAL_ADDRESS        CurrentAddress;\r
+  EFI_PHYSICAL_ADDRESS        EndOfFirmwareVolume;\r
+  EFI_FFS_FILE_HEADER         *File;\r
+  UINT32                      Size;\r
+  EFI_PHYSICAL_ADDRESS        EndOfFile;\r
+  EFI_COMMON_SECTION_HEADER   *Section;\r
+  EFI_PHYSICAL_ADDRESS        EndOfSection;\r
+\r
+  *SecCoreImageBase = 0;\r
+  *PeiCoreImageBase = 0;\r
+\r
+  CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) BootFirmwareVolumePtr;\r
+  EndOfFirmwareVolume = CurrentAddress + BootFirmwareVolumePtr->FvLength;\r
+\r
+  //\r
+  // Loop through the FFS files in the Boot Firmware Volume\r
+  //\r
+  for (EndOfFile = CurrentAddress + BootFirmwareVolumePtr->HeaderLength; ; ) {\r
+\r
+    CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;\r
+    if (CurrentAddress > EndOfFirmwareVolume) {\r
+      return EFI_NOT_FOUND;\r
+    }\r
+\r
+    File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;\r
+    if (IS_FFS_FILE2 (File)) {\r
+      Size = FFS_FILE2_SIZE (File);\r
+      if (Size <= 0x00FFFFFF) {\r
+        return EFI_NOT_FOUND;\r
+      }\r
+    } else {\r
+      Size = FFS_FILE_SIZE (File);\r
+      if (Size < sizeof (EFI_FFS_FILE_HEADER)) {\r
+        return EFI_NOT_FOUND;\r
+      }\r
+    }\r
+\r
+    EndOfFile = CurrentAddress + Size;\r
+    if (EndOfFile > EndOfFirmwareVolume) {\r
+      return EFI_NOT_FOUND;\r
+    }\r
+\r
+    //\r
+    // Look for SEC Core / PEI Core files\r
+    //\r
+    if (File->Type != EFI_FV_FILETYPE_SECURITY_CORE &&\r
+        File->Type != EFI_FV_FILETYPE_PEI_CORE) {\r
+      continue;\r
+    }\r
+\r
+    //\r
+    // Loop through the FFS file sections within the FFS file\r
+    //\r
+    if (IS_FFS_FILE2 (File)) {\r
+      EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER2));\r
+    } else {\r
+      EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER));\r
+    }\r
+    for (;;) {\r
+      CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;\r
+      Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;\r
+\r
+      if (IS_SECTION2 (Section)) {\r
+        Size = SECTION2_SIZE (Section);\r
+        if (Size <= 0x00FFFFFF) {\r
+          return EFI_NOT_FOUND;\r
+        }\r
+      } else {\r
+        Size = SECTION_SIZE (Section);\r
+        if (Size < sizeof (EFI_COMMON_SECTION_HEADER)) {\r
+          return EFI_NOT_FOUND;\r
+        }\r
+      }\r
+\r
+      EndOfSection = CurrentAddress + Size;\r
+      if (EndOfSection > EndOfFile) {\r
+        return EFI_NOT_FOUND;\r
+      }\r
+\r
+      //\r
+      // Look for executable sections\r
+      //\r
+      if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) {\r
+        if (File->Type == EFI_FV_FILETYPE_SECURITY_CORE) {\r
+          if (IS_SECTION2 (Section)) {\r
+            *SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
+          } else {\r
+            *SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
+          }\r
+        } else {\r
+          if (IS_SECTION2 (Section)) {\r
+            *PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
+          } else {\r
+            *PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
+          }\r
+        }\r
+        break;\r
+      }\r
+    }\r
+\r
+    //\r
+    // Both SEC Core and PEI Core images found\r
+    //\r
+    if (*SecCoreImageBase != 0 && *PeiCoreImageBase != 0) {\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  Find and return Pei Core entry point.\r
+\r
+  It also find SEC and PEI Core file debug information. It will report them if\r
+  remote debug is enabled.\r
+\r
+  @param   BootFirmwareVolumePtr    Point to the boot firmware volume.\r
+  @param   PeiCoreEntryPoint        The entry point of the PEI core.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FindAndReportEntryPoints (\r
+  IN  EFI_FIRMWARE_VOLUME_HEADER       *BootFirmwareVolumePtr,\r
+  OUT EFI_PEI_CORE_ENTRY_POINT         *PeiCoreEntryPoint\r
+  )\r
+{\r
+  EFI_STATUS                       Status;\r
+  EFI_PHYSICAL_ADDRESS             SecCoreImageBase;\r
+  EFI_PHYSICAL_ADDRESS             PeiCoreImageBase;\r
+  PE_COFF_LOADER_IMAGE_CONTEXT     ImageContext;\r
+\r
+  //\r
+  // Find SEC Core and PEI Core image base\r
+  //\r
+  Status = FindImageBase (BootFirmwareVolumePtr, &SecCoreImageBase, &PeiCoreImageBase);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  ZeroMem ((VOID *) &ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));\r
+  //\r
+  // Report SEC Core debug information when remote debug is enabled\r
+  //\r
+  ImageContext.ImageAddress = SecCoreImageBase;\r
+  ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+  PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
+\r
+  //\r
+  // Report PEI Core debug information when remote debug is enabled\r
+  //\r
+  ImageContext.ImageAddress = PeiCoreImageBase;\r
+  ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+  PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
+\r
+  //\r
+  // Find PEI Core entry point\r
+  //\r
+  Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);\r
+  if (EFI_ERROR (Status)) {\r
+    *PeiCoreEntryPoint = 0;\r
+  }\r
+\r
+  return;\r
+}\r

diff --git a/UefiCpuPkg/SecCore/Ia32/ResetVec.asm16 b/UefiCpuPkg/SecCore/Ia32/ResetVec.asm16
new file mode 100644 (file)
index 0000000..d90613c
--- /dev/null
+++ b/UefiCpuPkg/SecCore/Ia32/ResetVec.asm16
@@ -0,0 +1,106 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;  ResetVec.asm\r
+;\r
+; Abstract:\r
+;\r
+;  Reset Vector Data structure\r
+;  This structure is located at 0xFFFFFFC0\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    .model  tiny\r
+    .686p\r
+    .stack  0h\r
+    .code\r
+\r
+;\r
+; The layout of this file is fixed. The build tool makes assumption of the layout.\r
+;\r
+\r
+    ORG     0h\r
+;\r
+; Reserved\r
+;\r
+ReservedData         DD 0eeeeeeeeh, 0eeeeeeeeh\r
+\r
+    ORG     10h\r
+;\r
+; This is located at 0xFFFFFFD0h\r
+;\r
+    mov     di, "AP"\r
+    jmp     ApStartup\r
+\r
+    ORG     20h\r
+;\r
+; Pointer to the entry point of the PEI core\r
+; It is located at 0xFFFFFFE0, and is fixed up by some build tool\r
+; So if the value 8..1 appears in the final FD image, tool failure occurs.\r
+;\r
+PeiCoreEntryPoint       DD      87654321h\r
+\r
+;\r
+; This is the handler for all kinds of exceptions. Since it's for debugging\r
+; purpose only, nothing except a dead loop would be done here. Developers could\r
+; analyze the cause of the exception if a debugger had been attached.\r
+;\r
+InterruptHandler    PROC\r
+    jmp     $\r
+    iret\r
+InterruptHandler    ENDP\r
+\r
+    ORG     30h\r
+;\r
+; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte\r
+; Execution starts here upon power-on/platform-reset.\r
+;\r
+ResetHandler:\r
+    nop\r
+    nop\r
+ApStartup:\r
+    ;\r
+    ; Jmp Rel16 instruction\r
+    ; Use machine code directly in case of the assembler optimization\r
+    ; SEC entry point relative address will be fixed up by some build tool.\r
+    ;\r
+    ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in\r
+    ; SecEntry.asm\r
+    ;\r
+    DB      0e9h\r
+    DW      -3\r
+\r
+\r
+    ORG     38h\r
+;\r
+; Ap reset vector segment address is at 0xFFFFFFF8\r
+; This will be fixed up by some build tool,\r
+; so if the value 1..8 appears in the final FD image,\r
+; tool failure occurs\r
+;\r
+ApSegAddress    dd      12345678h\r
+\r
+    ORG     3ch\r
+;\r
+; BFV Base is at 0xFFFFFFFC\r
+; This will be fixed up by some build tool,\r
+; so if the value 1..8 appears in the final FD image,\r
+; tool failure occurs.\r
+;\r
+BfvBase     DD      12345678h\r
+\r
+;\r
+; Nothing can go here, otherwise the layout of this file would change.\r
+;\r
+\r
+    END\r

diff --git a/UefiCpuPkg/SecCore/Ia32/ResetVec.nasmb b/UefiCpuPkg/SecCore/Ia32/ResetVec.nasmb
new file mode 100644 (file)
index 0000000..2fcdc85
--- /dev/null
+++ b/UefiCpuPkg/SecCore/Ia32/ResetVec.nasmb
@@ -0,0 +1,103 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;  ResetVec.nasmb\r
+;\r
+; Abstract:\r
+;\r
+;  Reset Vector Data structure\r
+;  This structure is located at 0xFFFFFFC0\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+;    .stack  0x0\r
+;    SECTION .text\r
+USE16\r
+\r
+;\r
+; The layout of this file is fixed. The build tool makes assumption of the layout.\r
+;\r
+\r
+    ORG     0h\r
+;\r
+; Reserved\r
+;\r
+ReservedData:            DD 0eeeeeeeeh, 0eeeeeeeeh\r
+\r
+    TIMES 0x10-($-$$) DB 0\r
+;\r
+; This is located at 0xFFFFFFD0h\r
+;\r
+    mov     di, "PA"\r
+    jmp     ApStartup\r
+\r
+    TIMES 0x20-($-$$) DB 0\r
+;\r
+; Pointer to the entry point of the PEI core\r
+; It is located at 0xFFFFFFE0, and is fixed up by some build tool\r
+; So if the value 8..1 appears in the final FD image, tool failure occurs.\r
+;\r
+PeiCoreEntryPoint:       DD      87654321h\r
+\r
+;\r
+; This is the handler for all kinds of exceptions. Since it's for debugging\r
+; purpose only, nothing except a dead loop would be done here. Developers could\r
+; analyze the cause of the exception if a debugger had been attached.\r
+;\r
+global ASM_PFX(InterruptHandler)\r
+ASM_PFX(InterruptHandler):\r
+    jmp     $\r
+    iret\r
+\r
+    TIMES 0x30-($-$$) DB 0\r
+;\r
+; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte\r
+; Execution starts here upon power-on/platform-reset.\r
+;\r
+ResetHandler:\r
+    nop\r
+    nop\r
+ApStartup:\r
+    ;\r
+    ; Jmp Rel16 instruction\r
+    ; Use machine code directly in case of the assembler optimization\r
+    ; SEC entry point relative address will be fixed up by some build tool.\r
+    ;\r
+    ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in\r
+    ; SecEntry.asm\r
+    ;\r
+    DB      0e9h\r
+    DW      -3\r
+\r
+\r
+    TIMES 0x38-($-$$) DB 0\r
+;\r
+; Ap reset vector segment address is at 0xFFFFFFF8\r
+; This will be fixed up by some build tool,\r
+; so if the value 1..8 appears in the final FD image,\r
+; tool failure occurs\r
+;\r
+ApSegAddress:    dd      12345678h\r
+\r
+    TIMES 0x3c-($-$$) DB 0\r
+;\r
+; BFV Base is at 0xFFFFFFFC\r
+; This will be fixed up by some build tool,\r
+; so if the value 1..8 appears in the final FD image,\r
+; tool failure occurs.\r
+;\r
+BfvBase:     DD      12345678h\r
+\r
+;\r
+; Nothing can go here, otherwise the layout of this file would change.\r
+;\r

diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf
new file mode 100644 (file)
index 0000000..bf08a4c
--- /dev/null
+++ b/UefiCpuPkg/SecCore/SecCore.inf
@@ -0,0 +1,72 @@
+## @file\r
+#  SecCore module that implements the SEC phase.\r
+#\r
+#  This is the first module taking control of the platform upon power-on/reset.\r
+#  It implements the first phase of the security phase. The entry point function is\r
+#  _ModuleEntryPoint in PlatformSecLib. The entry point function will switch to\r
+#  protected mode, setup flat memory model, enable temporary memory and\r
+#  call into SecStartup().\r
+#\r
+#  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution.  The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SecCore\r
+  MODULE_UNI_FILE                = SecCore.uni\r
+  FILE_GUID                      = 1BA0062E-C779-4582-8566-336AE8F78F09\r
+  MODULE_TYPE                    = SEC\r
+  VERSION_STRING                 = 1.0\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  SecMain.c\r
+  SecMain.h\r
+  FindPeiCore.c\r
+\r
+[Sources.IA32]\r
+  Ia32/ResetVec.asm16 | MSFT\r
+  Ia32/ResetVec.asm16 | INTEL\r
+  Ia32/ResetVec.nasmb | GCC\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  UefiCpuPkg/UefiCpuPkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseMemoryLib\r
+  DebugLib\r
+  BaseLib\r
+  PlatformSecLib\r
+  PcdLib\r
+  DebugAgentLib\r
+  UefiCpuLib\r
+  PeCoffGetEntryPointLib\r
+  PeCoffExtraActionLib\r
+  CpuExceptionHandlerLib\r
+  ReportStatusCodeLib\r
+\r
+[Ppis]\r
+  gEfiSecPlatformInformationPpiGuid                    ## PRODUCES\r
+  gEfiTemporaryRamDonePpiGuid                          ## PRODUCES\r
+\r
+[Pcd]\r
+  gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize  ## CONSUMES\r
+\r
+[UserExtensions.TianoCore."ExtraFiles"]\r
+  SecCoreExtra.uni\r

diff --git a/UefiCpuPkg/SecCore/SecCore.uni b/UefiCpuPkg/SecCore/SecCore.uni
new file mode 100644 (file)
index 0000000..dff756a
Binary files /dev/null and b/UefiCpuPkg/SecCore/SecCore.uni differ

diff --git a/UefiCpuPkg/SecCore/SecCoreExtra.uni b/UefiCpuPkg/SecCore/SecCoreExtra.uni
new file mode 100644 (file)
index 0000000..15e22ed
Binary files /dev/null and b/UefiCpuPkg/SecCore/SecCoreExtra.uni differ

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
new file mode 100644 (file)
index 0000000..ec252cf
--- /dev/null
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -0,0 +1,295 @@
+/** @file\r
+  C functions in SEC\r
+\r
+  Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "SecMain.h"\r
+\r
+EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi = {\r
+  SecTemporaryRamDone\r
+};\r
+\r
+EFI_SEC_PLATFORM_INFORMATION_PPI  mSecPlatformInformationPpi = { SecPlatformInformation };\r
+\r
+EFI_PEI_PPI_DESCRIPTOR            mPeiSecPlatformInformationPpi[] = {\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+    &gEfiTemporaryRamDonePpiGuid,\r
+    &gSecTemporaryRamDonePpi\r
+  },\r
+  {\r
+    (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+    &gEfiSecPlatformInformationPpiGuid,\r
+    &mSecPlatformInformationPpi\r
+  }\r
+};\r
+\r
+//\r
+// These are IDT entries pointing to 10:FFFFFFE4h.\r
+//\r
+UINT64  mIdtEntryTemplate = 0xffff8e000010ffe4ULL;\r
+\r
+/**\r
+  Caller provided function to be invoked at the end of InitializeDebugAgent().\r
+\r
+  Entry point to the C language phase of SEC. After the SEC assembly\r
+  code has initialized some temporary memory and set up the stack,\r
+  the control is transferred to this function.\r
+\r
+  @param[in] Context    The first input parameter of InitializeDebugAgent().\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartupPhase2(\r
+  IN VOID                     *Context\r
+  );\r
+\r
+/**\r
+\r
+  Entry point to the C language phase of SEC. After the SEC assembly\r
+  code has initialized some temporary memory and set up the stack,\r
+  the control is transferred to this function.\r
+\r
+\r
+  @param SizeOfRam           Size of the temporary memory available for use.\r
+  @param TempRamBase         Base address of temporary ram\r
+  @param BootFirmwareVolume  Base address of the Boot Firmware Volume.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartup (\r
+  IN UINT32                   SizeOfRam,\r
+  IN UINT32                   TempRamBase,\r
+  IN VOID                     *BootFirmwareVolume\r
+  )\r
+{\r
+  EFI_SEC_PEI_HAND_OFF        SecCoreData;\r
+  IA32_DESCRIPTOR             IdtDescriptor;\r
+  SEC_IDT_TABLE               IdtTableInStack;\r
+  UINT32                      Index;\r
+  UINT32                      PeiStackSize;\r
+  EFI_STATUS                  Status;\r
+\r
+  //\r
+  // Report Status Code to indicate entering SEC core\r
+  //\r
+  REPORT_STATUS_CODE (\r
+    EFI_PROGRESS_CODE,\r
+    EFI_SOFTWARE_SEC | EFI_SW_SEC_PC_ENTRY_POINT\r
+    );\r
+\r
+  PeiStackSize = PcdGet32 (PcdPeiTemporaryRamStackSize);\r
+  if (PeiStackSize == 0) {\r
+    PeiStackSize = (SizeOfRam >> 1);\r
+  }\r
+\r
+  ASSERT (PeiStackSize < SizeOfRam);\r
+\r
+  //\r
+  // Process all libraries constructor function linked to SecCore.\r
+  //\r
+  ProcessLibraryConstructorList ();\r
+\r
+  //\r
+  // Initialize floating point operating environment\r
+  // to be compliant with UEFI spec.\r
+  //\r
+  InitializeFloatingPointUnits ();\r
+\r
+  // |-------------------|---->\r
+  // |IDT Table          |\r
+  // |-------------------|\r
+  // |PeiService Pointer |    PeiStackSize\r
+  // |-------------------|\r
+  // |                   |\r
+  // |      Stack        |\r
+  // |-------------------|---->\r
+  // |                   |\r
+  // |                   |\r
+  // |      Heap         |    PeiTemporayRamSize\r
+  // |                   |\r
+  // |                   |\r
+  // |-------------------|---->  TempRamBase\r
+\r
+  IdtTableInStack.PeiService = 0;\r
+  for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {\r
+    CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64));\r
+  }\r
+\r
+  IdtDescriptor.Base  = (UINTN) &IdtTableInStack.IdtTable;\r
+  IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);\r
+\r
+  AsmWriteIdtr (&IdtDescriptor);\r
+\r
+  //\r
+  // Setup the default exception handlers\r
+  //\r
+  Status = InitializeCpuExceptionHandlers (NULL);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Update the base address and length of Pei temporary memory\r
+  //\r
+  SecCoreData.DataSize               = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);\r
+  SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;\r
+  SecCoreData.BootFirmwareVolumeSize = (UINTN)(0x100000000ULL - (UINTN) BootFirmwareVolume);\r
+  SecCoreData.TemporaryRamBase       = (VOID*)(UINTN) TempRamBase;\r
+  SecCoreData.TemporaryRamSize       = SizeOfRam;\r
+  SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
+  SecCoreData.PeiTemporaryRamSize    = SizeOfRam - PeiStackSize;\r
+  SecCoreData.StackBase              = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);\r
+  SecCoreData.StackSize              = PeiStackSize;\r
+\r
+  //\r
+  // Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.\r
+  //\r
+  InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);\r
+}\r
+\r
+/**\r
+  Caller provided function to be invoked at the end of InitializeDebugAgent().\r
+\r
+  Entry point to the C language phase of SEC. After the SEC assembly\r
+  code has initialized some temporary memory and set up the stack,\r
+  the control is transferred to this function.\r
+\r
+  @param[in] Context    The first input parameter of InitializeDebugAgent().\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartupPhase2(\r
+  IN VOID                     *Context\r
+  )\r
+{\r
+  EFI_SEC_PEI_HAND_OFF        *SecCoreData;\r
+  EFI_PEI_PPI_DESCRIPTOR      *PpiList;\r
+  UINT32                      Index;\r
+  EFI_PEI_PPI_DESCRIPTOR      *AllSecPpiList;\r
+  EFI_PEI_CORE_ENTRY_POINT    PeiCoreEntryPoint;\r
+\r
+  SecCoreData   = (EFI_SEC_PEI_HAND_OFF *) Context;\r
+  AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *) SecCoreData->PeiTemporaryRamBase;\r
+  //\r
+  // Find Pei Core entry point. It will report SEC and Pei Core debug information if remote debug\r
+  // is enabled.\r
+  //\r
+  FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);\r
+  if (PeiCoreEntryPoint == NULL)\r
+  {\r
+    CpuDeadLoop ();\r
+  }\r
+\r
+  //\r
+  // Perform platform specific initialization before entering PeiCore.\r
+  //\r
+  PpiList = SecPlatformMain (SecCoreData);\r
+  if (PpiList != NULL) {\r
+    //\r
+    // Remove the terminal flag from the terminal PPI\r
+    //\r
+    CopyMem (AllSecPpiList, mPeiSecPlatformInformationPpi, sizeof (mPeiSecPlatformInformationPpi));\r
+    Index = sizeof (mPeiSecPlatformInformationPpi) / sizeof (EFI_PEI_PPI_DESCRIPTOR) - 1;\r
+    AllSecPpiList[Index].Flags = AllSecPpiList[Index].Flags & (~EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
+\r
+    //\r
+    // Append the platform additional PPI list\r
+    //\r
+    Index += 1;\r
+    while (((PpiList->Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST)) {\r
+      CopyMem (&AllSecPpiList[Index], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+      Index++;\r
+      PpiList++;\r
+    }\r
+\r
+    //\r
+    // Add the terminal PPI\r
+    //\r
+    CopyMem (&AllSecPpiList[Index ++], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+\r
+    //\r
+    // Set PpiList to the total PPI\r
+    //\r
+    PpiList = AllSecPpiList;\r
+\r
+    //\r
+    // Adjust PEI TEMP RAM Range.\r
+    //\r
+    ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+    SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+    SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR);\r
+  } else {\r
+    //\r
+    // No addition PPI, PpiList directly point to the common PPI list.\r
+    //\r
+    PpiList = &mPeiSecPlatformInformationPpi[0];\r
+  }\r
+\r
+  //\r
+  // Report Status Code to indicate transferring to PEI core\r
+  //\r
+  REPORT_STATUS_CODE (\r
+    EFI_PROGRESS_CODE,\r
+    EFI_SOFTWARE_SEC | EFI_SW_SEC_PC_HANDOFF_TO_NEXT\r
+    );\r
+\r
+  //\r
+  // Transfer the control to the PEI core\r
+  //\r
+  ASSERT (PeiCoreEntryPoint != NULL);\r
+  (*PeiCoreEntryPoint) (SecCoreData, PpiList);\r
+\r
+  //\r
+  // Should not come here.\r
+  //\r
+  return;\r
+}\r
+\r
+/**\r
+  TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked\r
+  by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.\r
+\r
+  @retval EFI_SUCCESS           Use of Temporary RAM was disabled.\r
+  @retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamDone (\r
+  VOID\r
+  )\r
+{\r
+  BOOLEAN  State;\r
+\r
+  //\r
+  // Migrate DebugAgentContext.\r
+  //\r
+  InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
+\r
+  //\r
+  // Disable interrupts and save current interrupt state\r
+  //\r
+  State = SaveAndDisableInterrupts();\r
+\r
+  //\r
+  // Disable Temporary RAM after Stack and Heap have been migrated at this point.\r
+  //\r
+  SecPlatformDisableTemporaryMemory ();\r
+\r
+  //\r
+  // Restore original interrupt state\r
+  //\r
+  SetInterruptState (State);\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h
new file mode 100644 (file)
index 0000000..05175d2
--- /dev/null
+++ b/UefiCpuPkg/SecCore/SecMain.h
@@ -0,0 +1,109 @@
+/** @file\r
+  Master header file for SecCore.\r
+\r
+  Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SEC_CORE_H_\r
+#define _SEC_CORE_H_\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/SecPlatformInformation.h>\r
+#include <Ppi/TemporaryRamDone.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/PlatformSecLib.h>\r
+#include <Library/UefiCpuLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/PeCoffExtraActionLib.h>\r
+#include <Library/DebugAgentLib.h>\r
+#include <Library/CpuExceptionHandlerLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+\r
+\r
+#define SEC_IDT_ENTRY_COUNT  34\r
+\r
+typedef struct _SEC_IDT_TABLE {\r
+  //\r
+  // Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base\r
+  // address should be 8-byte alignment.\r
+  // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store\r
+  // EFI_PEI_SERVICES**\r
+  //\r
+  UINT64            PeiService;\r
+  UINT64            IdtTable[SEC_IDT_ENTRY_COUNT];\r
+} SEC_IDT_TABLE;\r
+\r
+/**\r
+  TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked\r
+  by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.\r
+\r
+  @retval EFI_SUCCESS           Use of Temporary RAM was disabled.\r
+  @retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamDone (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Entry point to the C language phase of SEC. After the SEC assembly\r
+  code has initialized some temporary memory and set up the stack,\r
+  the control is transferred to this function.\r
+\r
+  @param SizeOfRam           Size of the temporary memory available for use.\r
+  @param TempRamBase         Base address of temporary ram\r
+  @param BootFirmwareVolume  Base address of the Boot Firmware Volume.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartup (\r
+  IN UINT32                   SizeOfRam,\r
+  IN UINT32                   TempRamBase,\r
+  IN VOID                     *BootFirmwareVolume\r
+  );\r
+\r
+/**\r
+  Find and return Pei Core entry point.\r
+\r
+  It also find SEC and PEI Core file debug information. It will report them if\r
+  remote debug is enabled.\r
+\r
+  @param  BootFirmwareVolumePtr  Point to the boot firmware volume.\r
+  @param  PeiCoreEntryPoint      Point to the PEI core entry point.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FindAndReportEntryPoints (\r
+  IN  EFI_FIRMWARE_VOLUME_HEADER       *BootFirmwareVolumePtr,\r
+  OUT EFI_PEI_CORE_ENTRY_POINT         *PeiCoreEntryPoint\r
+  );\r
+\r
+/**\r
+  Auto-generated function that calls the library constructors for all of the module's\r
+  dependent libraries.  This function must be called by the SEC Core once a stack has\r
+  been established.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ProcessLibraryConstructorList (\r
+  VOID\r
+  );\r
+\r
+#endif\r