UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo

Change the variable name from mInternalGr3 to mInternalCr3.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index ebfc46ad459bde22960fc6536a0ad5e2f840a186..d67f036aea69a3bbc04410408c4ca518390249e6 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -32,7 +32,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
   {Page1G,  SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},\r
 };\r
 \r
-UINTN  mInternalGr3;\r
+UINTN  mInternalCr3;\r
 \r
 /**\r
   Set the internal page table base address.\r
@@ -46,7 +46,7 @@ SetPageTableBase (
   IN UINTN   Cr3\r
   )\r
 {\r
-  mInternalGr3 = Cr3;\r
+  mInternalCr3 = Cr3;\r
 }\r
 \r
 /**\r
@@ -59,8 +59,8 @@ GetPageTableBase (
   VOID\r
   )\r
 {\r
-  if (mInternalGr3 != 0) {\r
-    return mInternalGr3;\r
+  if (mInternalCr3 != 0) {\r
+    return mInternalCr3;\r
   }\r
   return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);\r
 }\r
@@ -252,7 +252,7 @@ ConvertPageEntryAttribute (
   if ((Attributes & EFI_MEMORY_RO) != 0) {\r
     if (IsSet) {\r
       NewPageEntry &= ~(UINT64)IA32_PG_RW;\r
-      if (mInternalGr3 != 0) {\r
+      if (mInternalCr3 != 0) {\r
         // Environment setup\r
         // ReadOnly page need set Dirty bit for shadow stack\r
         NewPageEntry |= IA32_PG_D;\r