/** @file\r
The file for AHCI mode of ATA host controller.\r
- \r
+\r
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
UINT32 Data;\r
\r
ASSERT (PciIo != NULL);\r
- \r
+\r
Data = 0;\r
\r
PciIo->Mem.Read (\r
)\r
{\r
UINT32 Data;\r
- \r
+\r
ASSERT (PciIo != NULL);\r
\r
Data = AhciReadReg (PciIo, Offset);\r
\r
/**\r
Wait for the value of the specified MMIO register set to the test value.\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param Offset The MMIO address to test.\r
@param MaskValue The mask value of memory.\r
IN UINT64 Timeout\r
)\r
{\r
- UINT32 Value; \r
+ UINT32 Value;\r
UINT32 Delay;\r
\r
Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
\r
/**\r
Wait for the value of the specified system memory set to the test value.\r
- \r
+\r
@param Address The system memory address to test.\r
@param MaskValue The mask value of memory.\r
@param TestValue The test value of memory.\r
IN UINT64 Timeout\r
)\r
{\r
- UINT32 Value; \r
+ UINT32 Value;\r
UINT32 Delay;\r
\r
Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
\r
/**\r
Check the memory status to the test value.\r
- \r
+\r
@param[in] Address The memory address to test.\r
@param[in] MaskValue The mask value of memory.\r
@param[in] TestValue The test value of memory.\r
if (RetryTimes != NULL) {\r
(*RetryTimes)--;\r
}\r
- \r
+\r
Value = *(volatile UINT32 *) Address;\r
Value &= MaskValue;\r
\r
}\r
\r
/**\r
- Check if the device is still on port. It also checks if the AHCI controller \r
+ Check if the device is still on port. It also checks if the AHCI controller\r
supports the address and data count will be transferred.\r
\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
\r
- @retval EFI_SUCCESS The device is attached to port and the transfer data is \r
+ @retval EFI_SUCCESS The device is attached to port and the transfer data is\r
supported by AHCI controller.\r
@retval EFI_UNSUPPORTED The transfer address and count is not supported by AHCI\r
controller.\r
\r
Clear the port interrupt and error status. It will also clear\r
HBA interrupt status.\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
- \r
-**/ \r
+\r
+**/\r
VOID\r
EFIAPI\r
AhciClearPortStatus (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Port\r
- ) \r
+ )\r
{\r
UINT32 Offset;\r
\r
\r
/**\r
Enable the FIS running for giving port.\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
@param Timeout The timeout value of enabling FIS, uses 100ns as a unit.\r
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);\r
\r
return AhciWaitMmioSet (\r
- PciIo, \r
+ PciIo,\r
Offset,\r
EFI_AHCI_PORT_CMD_FR,\r
EFI_AHCI_PORT_CMD_FR,\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Port,\r
IN UINT64 Timeout\r
- ) \r
+ )\r
{\r
UINT32 Offset;\r
UINT32 Data;\r
if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) != 0) {\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
//\r
// Check if the Fis receive DMA engine for the port is running.\r
//\r
\r
/**\r
Build the command list, command table and prepare the fis receiver.\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
@param DataPhysicalAddr The pointer to the data buffer pci bus master address.\r
@param DataLength The data count to be transferred.\r
\r
-**/ \r
+**/\r
VOID\r
EFIAPI\r
AhciBuildCommand (\r
IN UINT8 CommandSlotNumber,\r
IN OUT VOID *DataPhysicalAddr,\r
IN UINT64 DataLength\r
- ) \r
+ )\r
{\r
UINT64 BaseAddr;\r
UINT64 PrdtNumber;\r
\r
//\r
// Filling the PRDT\r
- // \r
+ //\r
PrdtNumber = (DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1) / EFI_AHCI_MAX_DATA_PER_PRDT;\r
\r
//\r
Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;\r
\r
BaseAddr = Data64.Uint64;\r
- \r
+\r
ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));\r
- \r
+\r
ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));\r
\r
CommandFis->AhciCFisPmNum = PortMultiplier;\r
- \r
+\r
CopyMem (&AhciRegisters->AhciCommandTable->CommandFis, CommandFis, sizeof (EFI_AHCI_COMMAND_FIS));\r
\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
} else {\r
AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));\r
}\r
- \r
+\r
RemainedData = (UINTN) DataLength;\r
MemAddr = (UINTN) DataPhysicalAddr;\r
CommandList->AhciCmdPrdtl = (UINT32)PrdtNumber;\r
- \r
+\r
for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {\r
if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {\r
AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;\r
(VOID *) ((UINTN) AhciRegisters->AhciCmdList + (UINTN) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),\r
CommandList,\r
sizeof (EFI_AHCI_COMMAND_LIST)\r
- ); \r
+ );\r
\r
Data64.Uint64 = (UINT64)(UINTN) AhciRegisters->AhciCommandTablePciAddr;\r
AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba = Data64.Uint32.Lower32;\r
\r
/**\r
Buid a command FIS.\r
- \r
+\r
@param CmdFis A pointer to the EFI_AHCI_COMMAND_FIS data structure.\r
@param AtaCommandBlock A pointer to the AhciBuildCommandFis data structure.\r
\r
//\r
// Indicator it's a command\r
//\r
- CmdFis->AhciCFisCmdInd = 0x1; \r
+ CmdFis->AhciCFisCmdInd = 0x1;\r
CmdFis->AhciCFisCmd = AtaCommandBlock->AtaCommand;\r
\r
CmdFis->AhciCFisFeature = AtaCommandBlock->AtaFeatures;\r
\r
/**\r
Start a PIO data transfer on specific port.\r
- \r
+\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param[in] Port The number of port.\r
IN UINT8 Port,\r
IN UINT8 PortMultiplier,\r
IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,\r
- IN UINT8 AtapiCommandLength, \r
- IN BOOLEAN Read, \r
+ IN UINT8 AtapiCommandLength,\r
+ IN BOOLEAN Read,\r
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
IN OUT VOID *MemoryAddr,\r
EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
UINT32 Delay;\r
EFI_AHCI_COMMAND_FIS CFis;\r
- EFI_AHCI_COMMAND_LIST CmdList; \r
+ EFI_AHCI_COMMAND_LIST CmdList;\r
UINT32 PortTfd;\r
UINT32 PrdCount;\r
\r
if (EFI_ERROR (Status) || (DataCount != MapLength)) {\r
return EFI_BAD_BUFFER_SIZE;\r
}\r
- \r
+\r
//\r
// Package read needed\r
//\r
0,\r
(VOID *)(UINTN)PhyAddr,\r
DataCount\r
- ); \r
- \r
+ );\r
+\r
Status = AhciStartCommand (\r
PciIo,\r
Port,\r
Port,\r
Timeout\r
);\r
- \r
+\r
AhciDisableFisReceive (\r
PciIo,\r
Port,\r
IN UINT8 PortMultiplier,\r
IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,\r
IN UINT8 AtapiCommandLength,\r
- IN BOOLEAN Read, \r
+ IN BOOLEAN Read,\r
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
IN OUT VOID *MemoryAddr,\r
// BlockIO tasks.\r
// Delay 100us to simulate the blocking time out checking.\r
//\r
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {\r
- OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
AsyncNonBlockingTransferRoutine (NULL, Instance);\r
- gBS->RestoreTPL (OldTpl); \r
//\r
// Stall for 100us.\r
//\r
MicroSecondDelay (100);\r
}\r
+ gBS->RestoreTPL (OldTpl);\r
\r
if ((Task == NULL) || ((Task != NULL) && (!Task->IsStart))) {\r
//\r
//\r
// For Blocking mode, the command should be stopped, the Fis should be disabled\r
// and the PciIo should be unmapped.\r
- // For non-blocking mode, only when a error is happened (if the return status is \r
- // EFI_NOT_READY that means the command doesn't finished, try again.), first do the \r
+ // For non-blocking mode, only when a error is happened (if the return status is\r
+ // EFI_NOT_READY that means the command doesn't finished, try again.), first do the\r
// context cleanup, then set the packet's Asb status.\r
//\r
if (Task == NULL ||\r
((Task != NULL) && (Status != EFI_NOT_READY))\r
) {\r
AhciStopCommand (\r
- PciIo, \r
+ PciIo,\r
Port,\r
Timeout\r
);\r
\r
AhciDisableFisReceive (\r
- PciIo, \r
+ PciIo,\r
Port,\r
Timeout\r
);\r
\r
/**\r
Start a non data transfer on specific port.\r
- \r
+\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param[in] Port The number of port.\r
@retval EFI_UNSUPPORTED The device is not ready for transfer.\r
@retval EFI_SUCCESS The non data transfer executes successfully.\r
\r
-**/ \r
+**/\r
EFI_STATUS\r
EFIAPI\r
AhciNonDataTransfer (\r
\r
/**\r
Stop command running for giving port\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
@param Timeout The timeout value of stop, uses 100ns as a unit.\r
- \r
+\r
@retval EFI_DEVICE_ERROR The command stop unsuccessfully.\r
@retval EFI_TIMEOUT The operation is time out.\r
@retval EFI_SUCCESS The command stop successfully.\r
);\r
\r
Status = AhciEnableFisReceive (\r
- PciIo, \r
+ PciIo,\r
Port,\r
Timeout\r
);\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
@param Timeout The timeout value of reset, uses 100ns as a unit.\r
- \r
+\r
@retval EFI_DEVICE_ERROR The port reset unsuccessfully\r
@retval EFI_TIMEOUT The reset operation is time out.\r
@retval EFI_SUCCESS The port reset successfully.\r
AhciReset (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT64 Timeout\r
- ) \r
+ )\r
{\r
UINT32 Delay;\r
UINT32 Value;\r
//\r
// S.M.A.R.T is not supported by the device\r
//\r
- DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n", \r
+ DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",\r
Port, PortMultiplier));\r
} else {\r
//\r
\r
/**\r
Send Buffer cmd to specific device.\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
IN EFI_AHCI_REGISTERS *AhciRegisters,\r
IN UINT8 Port,\r
IN UINT8 PortMultiplier,\r
- IN OUT EFI_IDENTIFY_DATA *Buffer \r
+ IN OUT EFI_IDENTIFY_DATA *Buffer\r
)\r
{\r
EFI_STATUS Status;\r
&AtaStatusBlock,\r
Buffer,\r
sizeof (EFI_IDENTIFY_DATA),\r
- ATA_ATAPI_TIMEOUT, \r
+ ATA_ATAPI_TIMEOUT,\r
NULL\r
);\r
\r
\r
/**\r
Send Buffer cmd to specific device.\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
IN EFI_AHCI_REGISTERS *AhciRegisters,\r
IN UINT8 Port,\r
IN UINT8 PortMultiplier,\r
- IN OUT EFI_IDENTIFY_DATA *Buffer \r
+ IN OUT EFI_IDENTIFY_DATA *Buffer\r
)\r
{\r
EFI_STATUS Status;\r
\r
/**\r
Send SET FEATURE cmd on specific device.\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
0,\r
&AtaCommandBlock,\r
&AtaStatusBlock,\r
- ATA_ATAPI_TIMEOUT, \r
+ ATA_ATAPI_TIMEOUT,\r
NULL\r
);\r
\r
}\r
\r
/**\r
- This function is used to send out ATAPI commands conforms to the Packet Command \r
+ This function is used to send out ATAPI commands conforms to the Packet Command\r
with PIO Protocol.\r
\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
- @param Port The number of port. \r
+ @param Port The number of port.\r
@param PortMultiplier The number of port multiplier.\r
@param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.\r
\r
Packet->CdbLength,\r
&AtaCommandBlock,\r
&AtaStatusBlock,\r
- Packet->Timeout, \r
+ Packet->Timeout,\r
NULL\r
);\r
} else {\r
&AtaStatusBlock,\r
Buffer,\r
Length,\r
- Packet->Timeout, \r
+ Packet->Timeout,\r
NULL\r
);\r
}\r
\r
/**\r
Allocate transfer-related data struct which is used at AHCI mode.\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
\r
\r
if (EFI_ERROR (Status) || (Bytes != MaxReceiveFisSize)) {\r
//\r
- // Map error or unable to map the whole RFis buffer into a contiguous region. \r
+ // Map error or unable to map the whole RFis buffer into a contiguous region.\r
//\r
Status = EFI_OUT_OF_RESOURCES;\r
goto Error6;\r
\r
if (EFI_ERROR (Status)) {\r
//\r
- // Free mapped resource. \r
+ // Free mapped resource.\r
//\r
Status = EFI_OUT_OF_RESOURCES;\r
goto Error5;\r
\r
if (EFI_ERROR (Status)) {\r
//\r
- // Free mapped resource. \r
+ // Free mapped resource.\r
//\r
Status = EFI_OUT_OF_RESOURCES;\r
goto Error3;\r
\r
return EFI_SUCCESS;\r
//\r
- // Map error or unable to map the whole CmdList buffer into a contiguous region. \r
+ // Map error or unable to map the whole CmdList buffer into a contiguous region.\r
//\r
Error1:\r
PciIo->Unmap (\r
/**\r
Initialize ATA host controller at AHCI mode.\r
\r
- The function is designed to initialize ATA host controller. \r
- \r
+ The function is designed to initialize ATA host controller.\r
+\r
@param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.\r
\r
**/\r
PciIo = Instance->PciIo;\r
IdeInit = Instance->IdeControllerInit;\r
\r
- Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT); \r
+ Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT);\r
\r
if (EFI_ERROR (Status)) {\r
return EFI_DEVICE_ERROR;\r
\r
//\r
// Get the bit map of those ports exposed by this HBA.\r
- // It indicates which ports that the HBA supports are available for software to use. \r
+ // It indicates which ports that the HBA supports are available for software to use.\r
//\r
PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);\r
- \r
+\r
AhciRegisters = &Instance->AhciRegisters;\r
Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);\r
\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- for (Port = 0; Port < MaxPortNumber; Port ++) { \r
+ for (Port = 0; Port < MaxPortNumber; Port ++) {\r
if ((PortImplementBitMap & (BIT0 << Port)) != 0) {\r
IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, Port);\r
\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);\r
Status = AhciWaitMmioSet (\r
- PciIo, \r
+ PciIo,\r
Offset,\r
EFI_AHCI_PORT_CMD_FR,\r
EFI_AHCI_PORT_CMD_FR,\r
MicroSecondDelay (1000);\r
PhyDetectDelay--;\r
} while (PhyDetectDelay > 0);\r
- \r
+\r
if (PhyDetectDelay == 0) {\r
continue;\r
}\r
//\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;\r
Status = AhciWaitMmioSet (\r
- PciIo, \r
+ PciIo,\r
Offset,\r
0x0000FFFF,\r
0x00000101,\r
} else {\r
continue;\r
}\r
- DEBUG ((EFI_D_INFO, "port [%d] port mulitplier [%d] has a [%a]\n", \r
+ DEBUG ((EFI_D_INFO, "port [%d] port mulitplier [%d] has a [%a]\n",\r
Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));\r
\r
//\r
TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);\r
} else if (SupportedModes->MultiWordDmaMode.Valid) {\r
TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;\r
- TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode; \r
+ TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;\r
}\r
\r
Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode));\r
/** @file\r
Header file for AHCI mode of ATA host controller.\r
- \r
+\r
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
read a one-byte data from a IDE port.\r
\r
@param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
- @param Port The IDE Port number \r
+ @param Port The IDE Port number\r
\r
@return the one-byte data read from IDE port\r
**/\r
}\r
/**\r
This function is used to poll for the DRQ bit set in the Alternate Status Register.\r
- DRQ is set when the device is ready to transfer data. So this function is called after \r
+ DRQ is set when the device is ready to transfer data. So this function is called after\r
the command is sent to the device and before required data is transferred.\r
\r
@param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
\r
/**\r
This function is used to poll for the DRDY bit set in the Status Register. DRDY\r
- bit is set when the device is ready to accept command. Most ATA commands must be \r
+ bit is set when the device is ready to accept command. Most ATA commands must be\r
sent after DRDY set except the ATAPI Packet Command.\r
\r
@param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
}\r
\r
/**\r
- This function is used to poll for the DRDY bit set in the Alternate Status Register. \r
- DRDY bit is set when the device is ready to accept command. Most ATA commands must \r
+ This function is used to poll for the DRDY bit set in the Alternate Status Register.\r
+ DRDY bit is set when the device is ready to accept command. Most ATA commands must\r
be sent after DRDY set except the ATAPI Packet Command.\r
\r
@param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
}\r
\r
/**\r
- Get IDE i/o port registers' base addresses by mode. \r
+ Get IDE i/o port registers' base addresses by mode.\r
\r
In 'Compatibility' mode, use fixed addresses.\r
In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's\r
|___________|_______________|_______________|\r
\r
Table 1. Compatibility resource mappings\r
- \r
+\r
b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs\r
in IDE controller's PCI Configuration Space, shown in the Table 2 below.\r
___________________________________________________\r
@param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance\r
@param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to\r
store the IDE i/o port registers' base addresses\r
- \r
+\r
@retval EFI_UNSUPPORTED Return this value when the BARs is not IO type\r
@retval EFI_SUCCESS Get the Base address successfully\r
@retval Other Read the pci configureation data error\r
\r
/**\r
This function is used to implement the Soft Reset on the specified device. But,\r
- the ATA Soft Reset mechanism is so strong a reset method that it will force \r
+ the ATA Soft Reset mechanism is so strong a reset method that it will force\r
resetting on both devices connected to the same cable.\r
\r
It is called by IdeBlkIoReset(), a interface function of Block\r
//\r
// Wait for at least 10 ms to check BSY status, we use 10 ms\r
// for better compatibility\r
- // \r
+ //\r
MicroSecondDelay (10000);\r
\r
//\r
@param[in] Timeout The time to complete the command, uses 100ns as a unit.\r
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
used by non-blocking mode.\r
- \r
+\r
@retval EFI_SUCCESS send out the ATA command and device send required data successfully.\r
@retval EFI_DEVICE_ERROR command sent failed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-AtaPioDataInOut ( \r
+AtaPioDataInOut (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN EFI_IDE_REGISTERS *IdeRegisters,\r
IN OUT VOID *Buffer,\r
// Poll DRQ bit set, data transfer can be performed only when DRQ is ready\r
//\r
Status = DRQReady2 (PciIo, IdeRegisters, Timeout);\r
- if (EFI_ERROR (Status)) { \r
+ if (EFI_ERROR (Status)) {\r
Status = EFI_DEVICE_ERROR;\r
goto Exit;\r
}\r
**/\r
EFI_STATUS\r
EFIAPI\r
-AtaNonDataCommandIn ( \r
+AtaNonDataCommandIn (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN EFI_IDE_REGISTERS *IdeRegisters,\r
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
Status = EFI_DEVICE_ERROR;\r
goto Exit;\r
}\r
- \r
+\r
Status = CheckStatusRegister (PciIo, IdeRegisters);\r
if (EFI_ERROR (Status)) {\r
Status = EFI_DEVICE_ERROR;\r
// Dump All Ide registers to ATA_STATUS_BLOCK\r
//\r
DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);\r
- \r
+\r
//\r
// Not support the Non-blocking now,just do the blocking process.\r
//\r
\r
/**\r
Wait for memory to be set.\r
- \r
+\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
\r
AtaUdmStatusWait (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN EFI_IDE_REGISTERS *IdeRegisters\r
- ) \r
+ )\r
{\r
UINT8 RegisterValue;\r
EFI_STATUS Status;\r
\r
/**\r
Check if the memory to be set.\r
- \r
+\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
used by non-blocking mode.\r
// BlockIO tasks.\r
// Delay 1ms to simulate the blocking time out checking.\r
//\r
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {\r
- OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
AsyncNonBlockingTransferRoutine (NULL, Instance);\r
- gBS->RestoreTPL (OldTpl);\r
//\r
// Stall for 1 milliseconds.\r
//\r
MicroSecondDelay (1000);\r
- } \r
+ }\r
+ gBS->RestoreTPL (OldTpl);\r
\r
//\r
// The data buffer should be even alignment\r
IoPortForBmid = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMID_OFFSET);\r
\r
//\r
- // For Blocking mode, start the command. \r
+ // For Blocking mode, start the command.\r
// For non-blocking mode, when the command is not started, start it, otherwise\r
// go to check the status.\r
- // \r
+ //\r
if (((Task != NULL) && (!Task->IsStart)) || (Task == NULL)) {\r
//\r
// Calculate the number of PRD entry.\r
}\r
IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);\r
\r
+ if (Task != NULL) {\r
+ //\r
+ // Max transfer number of sectors for one command is 65536(32Mbyte),\r
+ // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).\r
+ // So set the variable Count to 2000, for about 2 second Timeout time.\r
+ //\r
+ Task->RetryTimes = 2000;\r
+ Task->Map = BufferMap;\r
+ Task->TableMap = PrdTableMap;\r
+ Task->MapBaseAddress = PrdBaseAddr;\r
+ Task->PageCount = PageCount;\r
+ Task->IsStart = TRUE;\r
+ }\r
+\r
//\r
// Issue ATA command\r
//\r
RegisterValue |= BMIC_START;\r
IdeWritePortB(PciIo, IoPortForBmic, RegisterValue);\r
\r
- if (Task != NULL) {\r
- //\r
- // Max transfer number of sectors for one command is 65536(32Mbyte),\r
- // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).\r
- // So set the variable Count to 2000, for about 2 second Timeout time.\r
- //\r
- Task->RetryTimes = 2000;\r
- Task->Map = BufferMap;\r
- Task->TableMap = PrdTableMap;\r
- Task->MapBaseAddress = PrdBaseAddr;\r
- Task->PageCount = PageCount;\r
- Task->IsStart = TRUE;\r
- }\r
}\r
\r
//\r
//\r
DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);\r
}\r
- \r
+\r
return Status;\r
}\r
\r
while ((TempWordBuffer & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {\r
IdeReadPortWMultiple (\r
PciIo,\r
- IdeRegisters->Data, \r
- 1, \r
+ IdeRegisters->Data,\r
+ 1,\r
&TempWordBuffer\r
);\r
TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
}\r
\r
/**\r
- This function is called by AtaPacketCommandExecute(). \r
+ This function is called by AtaPacketCommandExecute().\r
It is used to transfer data between host and device. The data direction is specified\r
by the fourth parameter.\r
\r
if (ByteCount == 0) {\r
return EFI_SUCCESS;\r
}\r
- \r
+\r
PtrBuffer = Buffer;\r
RequiredWordCount = (UINT32)RShiftU64(ByteCount, 1);\r
//\r
PtrBuffer += WordCount;\r
ActualWordCount += WordCount;\r
}\r
- \r
+\r
if (Read) {\r
//\r
// In the case where the drive wants to send more data than we need to read,\r
if (EFI_ERROR (Status)) {\r
return EFI_DEVICE_ERROR;\r
}\r
- \r
+\r
return Status;\r
}\r
\r
}\r
\r
/**\r
- This function is used to send out ATAPI commands conforms to the Packet Command \r
+ This function is used to send out ATAPI commands conforms to the Packet Command\r
with PIO Data In Protocol.\r
\r
@param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance\r
// Send out ATAPI command packet\r
//\r
for (Count = 0; Count < 6; Count++) {\r
- IdeWritePortW (PciIo, IdeRegisters->Data, *((UINT16*)PacketCommand + Count)); \r
+ IdeWritePortW (PciIo, IdeRegisters->Data, *((UINT16*)PacketCommand + Count));\r
//\r
// Stall for 10 microseconds.\r
//\r
EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
\r
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
- \r
+\r
AtaCommandBlock.AtaCommand = ATA_CMD_INIT_DRIVE_PARAM;\r
AtaCommandBlock.AtaSectorCount = DriveParameters->Sector;\r
AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) + DriveParameters->Heads);\r
&Instance->IdeRegisters[Channel],\r
&AtaCommandBlock,\r
AtaStatusBlock,\r
- ATA_ATAPI_TIMEOUT, \r
+ ATA_ATAPI_TIMEOUT,\r
NULL\r
);\r
\r
&Instance->IdeRegisters[Channel],\r
&AtaCommandBlock,\r
AtaStatusBlock,\r
- ATA_ATAPI_TIMEOUT, \r
+ ATA_ATAPI_TIMEOUT,\r
NULL\r
);\r
\r
//\r
// S.M.A.R.T is not supported by the device\r
//\r
- DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at [%a] channel [%a] device!\n", \r
+ DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at [%a] channel [%a] device!\n",\r
(Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));\r
} else {\r
//\r
}\r
}\r
\r
- DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at [%a] channel [%a] device!\n", \r
+ DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at [%a] channel [%a] device!\n",\r
(Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));\r
\r
}\r
to fill in the Media data structure of the Block I/O Protocol interface.\r
\r
There are 5 steps to reach such objective:\r
- 1. Sends out the ATAPI Identify Command to the specified device. \r
+ 1. Sends out the ATAPI Identify Command to the specified device.\r
Only ATAPI device responses to this command. If the command succeeds,\r
- it returns the Identify data structure which filled with information \r
- about the device. Since the ATAPI device contains removable media, \r
+ it returns the Identify data structure which filled with information\r
+ about the device. Since the ATAPI device contains removable media,\r
the only meaningful information is the device module name.\r
2. Sends out ATAPI Inquiry Packet Command to the specified device.\r
This command will return inquiry data of the device, which contains\r
the device type information.\r
3. Allocate sense data space for future use. We don't detect the media\r
- presence here to improvement boot performance, especially when CD \r
+ presence here to improvement boot performance, especially when CD\r
media is present. The media detection will be performed just before\r
each BLK_IO read/write\r
- \r
+\r
@param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
@param Channel The channel number of device.\r
@param Device The device number of device.\r
EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
\r
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
- \r
+\r
AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;\r
AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);\r
\r
// This command should work no matter DRDY is ready or not\r
//\r
IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, ATA_CMD_EXEC_DRIVE_DIAG);\r
- \r
+\r
Status = WaitForBSYClear (PciIo, IdeRegisters, 350000000);\r
if (EFI_ERROR (Status)) {\r
DEBUG((EFI_D_ERROR, "New detecting method: Send Execute Diagnostic Command: WaitForBSYClear: Status: %d\n", Status));\r
continue;\r
}\r
\r
- DEBUG ((EFI_D_INFO, "[%a] channel [%a] [%a] device\n", \r
+ DEBUG ((EFI_D_INFO, "[%a] channel [%a] [%a] device\n",\r
(IdeChannel == 1) ? "secondary" : "primary ", (IdeDevice == 1) ? "slave " : "master",\r
DeviceType == EfiIdeCdrom ? "cdrom " : "harddisk"));\r
//\r
\r
/**\r
Initialize ATA host controller at IDE mode.\r
- \r
- The function is designed to initialize ATA host controller. \r
- \r
+\r
+ The function is designed to initialize ATA host controller.\r
+\r
@param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.\r
\r
**/\r
projects / mirror_edk2.git / commitdiff