]> git.proxmox.com Git - mirror_edk2.git/commitdiff
OvmfPkg: report support for the PIIX3 reset register in the FADT
authorjljusten <jljusten@6f19259b-4bc3-4df7-8a09-765794883524>
Mon, 4 Mar 2013 17:38:05 +0000 (17:38 +0000)
committerjljusten <jljusten@6f19259b-4bc3-4df7-8a09-765794883524>
Mon, 4 Mar 2013 17:38:05 +0000 (17:38 +0000)
The value to be written corresponds to hard reset, which is what the ACPI
spec prescribes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14156 6f19259b-4bc3-4df7-8a09-765794883524

OvmfPkg/AcpiTables/Facp.aslc
OvmfPkg/AcpiTables/Platform.h

index 9a17905c44382fd1a6ae461849929b85800cd547..df35285c9c918a793aa4a5db3483338d5d691c9d 100644 (file)
@@ -65,8 +65,8 @@ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
   0x0000,           // Boot architecture flag (16-bit)\r
   RESERVED,         // reserved\r
   FLAG,             // Fixed feature flags\r
-  { 0 },            // Address of the Reset Register\r
-  0,                // Value for the Reset Register to reset the system\r
+  GAS2_IO(RESET_REG, 1), // Extended address of the Reset Register\r
+  RESET_VALUE,           // Value for the Reset Register to reset the system\r
   { RESERVED },     // reserved[3]\r
   0,                // 64-bit physical addesss of FACS, set at installation\r
   0,                // 64-bit physical addesss of DSDT, set at installation\r
index c95cbb20d572f4df2eeb7e6be5f6c452ffd527f0..d96b847239668fc1131d6b1e8991606b1525eaec 100644 (file)
 #define FLAG            (EFI_ACPI_2_0_WBINVD | \\r
                          EFI_ACPI_2_0_PROC_C1 | \\r
                          EFI_ACPI_2_0_SLP_BUTTON | \\r
-                         EFI_ACPI_2_0_RTC_S4)\r
+                         EFI_ACPI_2_0_RTC_S4 | \\r
+                         EFI_ACPI_2_0_RESET_REG_SUP)\r
+#define RESET_REG       0xCF9\r
+#define RESET_VALUE     (BIT2 | BIT1) // PIIX3 Reset CPU + System Reset\r
 \r
 //\r
 // Byte-aligned IO port register block initializer for\r