MdeModulePkg/XhciPei:1ms delay before access MMIO reg during reset

Some XHCI host controllers require to have extra 1ms delay before
accessing any MMIO register during HC reset.

As this delay is not defined by XHCI spec, we use this workaround
to fix the issue.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
index a58739fb4a681edcfedfb76ab00a9a6c08dfc94c..57e70701e826dbea37357c41f62aeeb86bfe1241 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
@@ -407,6 +407,12 @@ XhcPeiResetHC (
   }\r
 \r
   XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
+  //\r
+  // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.\r
+  // Otherwise there may have the timeout case happened.\r
+  // The below is a workaround to solve such problem.\r
+  //\r
+  MicroSecondDelay (1000);\r
   Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
 ON_EXIT:\r
   DEBUG ((EFI_D_INFO, "XhcPeiResetHC: %r\n", Status));\r