MdePkg/BaseCacheMaintenanceLib: LoongArch cache maintenance implementation.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Implement LoongArch cache maintenance functions in
BaseCacheMaintenanceLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index 33114243d571a675ba80251646d5887918ea6813..6fd9cbe5f6c927040b87a38ca177eed919f47d60 100644 (file)
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -7,6 +7,7 @@
 #  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
 #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 #  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+#  Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>\r
 #\r
 #  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
@@ -24,7 +25,7 @@
 \r
 \r
 #\r
-#  VALID_ARCHITECTURES           = IA32 X64 EBC ARM AARCH64\r
+#  VALID_ARCHITECTURES           = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64\r
 #\r
 \r
 [Sources.IA32]\r
@@ -45,6 +46,9 @@
 [Sources.RISCV64]\r
   RiscVCache.c\r
 \r
+[Sources.LOONGARCH64]\r
+  LoongArchCache.c\r
+\r
 [Packages]\r
   MdePkg/MdePkg.dec\r
 \r

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c
new file mode 100644 (file)
index 0000000..4c87732
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c
@@ -0,0 +1,254 @@
+/** @file\r
+  Cache Maintenance Functions for LoongArch.\r
+  LoongArch cache maintenance functions has not yet been completed, and will added in later.\r
+  Functions are null functions now.\r
+\r
+  Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include <Base.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+/**\r
+  LoongArch data barrier operation.\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmDataBarrierLoongArch (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  LoongArch instruction barrier operation.\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmInstructionBarrierLoongArch (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Invalidates the entire instruction cache in cache coherency domain of the\r
+  calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InvalidateInstructionCache (\r
+  VOID\r
+  )\r
+{\r
+  AsmInstructionBarrierLoongArch ();\r
+}\r
+\r
+/**\r
+  Invalidates a range of instruction cache lines in the cache coherency domain\r
+  of the calling CPU.\r
+\r
+  Invalidates the instruction cache lines specified by Address and Length. If\r
+  Address is not aligned on a cache line boundary, then entire instruction\r
+  cache line containing Address is invalidated. If Address + Length is not\r
+  aligned on a cache line boundary, then the entire instruction cache line\r
+  containing Address + Length -1 is invalidated. This function may choose to\r
+  invalidate the entire instruction cache if that is more efficient than\r
+  invalidating the specified range. If Length is 0, the no instruction cache\r
+  lines are invalidated. Address is returned.\r
+\r
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+  @param[in]  Address The base address of the instruction cache lines to\r
+                  invalidate. If the CPU is in a physical addressing mode, then\r
+                  Address is a physical address. If the CPU is in a virtual\r
+                  addressing mode, then Address is a virtual address.\r
+\r
+  @param[in]  Length  The number of bytes to invalidate from the instruction cache.\r
+\r
+  @return Address.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateInstructionCacheRange (\r
+  IN       VOID   *Address,\r
+  IN       UINTN  Length\r
+  )\r
+{\r
+  AsmInstructionBarrierLoongArch ();\r
+  return Address;\r
+}\r
+\r
+/**\r
+  Writes Back and Invalidates the entire data cache in cache coherency domain\r
+  of the calling CPU.\r
+\r
+  Writes Back and Invalidates the entire data cache in cache coherency domain\r
+  of the calling CPU. This function guarantees that all dirty cache lines are\r
+  written back to system memory, and also invalidates all the data cache lines\r
+  in the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackInvalidateDataCache (\r
+  VOID\r
+  )\r
+{\r
+  DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));\r
+}\r
+\r
+/**\r
+  Writes Back and Invalidates a range of data cache lines in the cache\r
+  coherency domain of the calling CPU.\r
+\r
+  Writes Back and Invalidate the data cache lines specified by Address and\r
+  Length. If Address is not aligned on a cache line boundary, then entire data\r
+  cache line containing Address is written back and invalidated. If Address +\r
+  Length is not aligned on a cache line boundary, then the entire data cache\r
+  line containing Address + Length -1 is written back and invalidated. This\r
+  function may choose to write back and invalidate the entire data cache if\r
+  that is more efficient than writing back and invalidating the specified\r
+  range. If Length is 0, the no data cache lines are written back and\r
+  invalidated. Address is returned.\r
+\r
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+  @param[in]  Address The base address of the data cache lines to write back and\r
+                  invalidate. If the CPU is in a physical addressing mode, then\r
+                  Address is a physical address. If the CPU is in a virtual\r
+                  addressing mode, then Address is a virtual address.\r
+  @param[in]  Length  The number of bytes to write back and invalidate from the\r
+                  data cache.\r
+\r
+  @return Address of cache invalidation.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackInvalidateDataCacheRange (\r
+  IN      VOID   *Address,\r
+  IN      UINTN  Length\r
+  )\r
+{\r
+  DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));\r
+  return Address;\r
+}\r
+\r
+/**\r
+  Writes Back the entire data cache in cache coherency domain of the calling\r
+  CPU.\r
+\r
+  Writes Back the entire data cache in cache coherency domain of the calling\r
+  CPU. This function guarantees that all dirty cache lines are written back to\r
+  system memory. This function may also invalidate all the data cache lines in\r
+  the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackDataCache (\r
+  VOID\r
+  )\r
+{\r
+  WriteBackInvalidateDataCache ();\r
+}\r
+\r
+/**\r
+  Writes Back a range of data cache lines in the cache coherency domain of the\r
+  calling CPU.\r
+\r
+  Writes Back the data cache lines specified by Address and Length. If Address\r
+  is not aligned on a cache line boundary, then entire data cache line\r
+  containing Address is written back. If Address + Length is not aligned on a\r
+  cache line boundary, then the entire data cache line containing Address +\r
+  Length -1 is written back. This function may choose to write back the entire\r
+  data cache if that is more efficient than writing back the specified range.\r
+  If Length is 0, the no data cache lines are written back. This function may\r
+  also invalidate all the data cache lines in the specified range of the cache\r
+  coherency domain of the calling CPU. Address is returned.\r
+\r
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+  @param[in]  Address The base address of the data cache lines to write back. If\r
+                  the CPU is in a physical addressing mode, then Address is a\r
+                  physical address. If the CPU is in a virtual addressing\r
+                  mode, then Address is a virtual address.\r
+  @param[in]  Length  The number of bytes to write back from the data cache.\r
+\r
+  @return Address of cache written in main memory.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackDataCacheRange (\r
+  IN      VOID   *Address,\r
+  IN      UINTN  Length\r
+  )\r
+{\r
+  DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));\r
+  return Address;\r
+}\r
+\r
+/**\r
+  Invalidates the entire data cache in cache coherency domain of the calling\r
+  CPU.\r
+\r
+  Invalidates the entire data cache in cache coherency domain of the calling\r
+  CPU. This function must be used with care because dirty cache lines are not\r
+  written back to system memory. It is typically used for cache diagnostics. If\r
+  the CPU does not support invalidation of the entire data cache, then a write\r
+  back and invalidate operation should be performed on the entire data cache.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InvalidateDataCache (\r
+  VOID\r
+  )\r
+{\r
+  AsmDataBarrierLoongArch ();\r
+}\r
+\r
+/**\r
+  Invalidates a range of data cache lines in the cache coherency domain of the\r
+  calling CPU.\r
+\r
+  Invalidates the data cache lines specified by Address and Length. If Address\r
+  is not aligned on a cache line boundary, then entire data cache line\r
+  containing Address is invalidated. If Address + Length is not aligned on a\r
+  cache line boundary, then the entire data cache line containing Address +\r
+  Length -1 is invalidated. This function must never invalidate any cache lines\r
+  outside the specified range. If Length is 0, the no data cache lines are\r
+  invalidated. Address is returned. This function must be used with care\r
+  because dirty cache lines are not written back to system memory. It is\r
+  typically used for cache diagnostics. If the CPU does not support\r
+  invalidation of a data cache range, then a write back and invalidate\r
+  operation should be performed on the data cache range.\r
+\r
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+  @param[in]  Address The base address of the data cache lines to invalidate. If\r
+                  the CPU is in a physical addressing mode, then Address is a\r
+                  physical address. If the CPU is in a virtual addressing mode,\r
+                  then Address is a virtual address.\r
+  @param[in]  Length  The number of bytes to invalidate from the data cache.\r
+\r
+  @return Address.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateDataCacheRange (\r
+  IN      VOID   *Address,\r
+  IN      UINTN  Length\r
+  )\r
+{\r
+  AsmDataBarrierLoongArch ();\r
+  return Address;\r
+}\r