--- /dev/null
+#\r
+# Copyright (c) 2012, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = ArmVExpressPkg-CTA15-A7\r
+ PLATFORM_GUID = 0b511920-978d-4b34-acc0-3d9f8e6f9d81\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/ArmVExpress-CTA15-A7\r
+ SUPPORTED_ARCHITECTURES = ARM\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.fdf\r
+ DEFINE EDK2_SKIP_PEICORE=1\r
+\r
+!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc\r
+\r
+[LibraryClasses.common]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf\r
+ \r
+ ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf\r
+ NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf\r
+\r
+ #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf\r
+\r
+ # ARM PL390 General Interrupt Driver in Secure and Non-secure\r
+ ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
+\r
+ LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf\r
+ \r
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf \r
+ ArmSmcLib|ArmPlatformPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
+\r
+[BuildOptions]\r
+!ifdef $(ARM_BIGLITTLE_TC2)\r
+ RVCT:*_*_ARM_ARCHCC_FLAGS = -DARM_BIGLITTLE_TC2=1\r
+ RVCT:*_*_ARM_PP_FLAGS = -DARM_BIGLITTLE_TC2=1\r
+\r
+ GCC:*_*_ARM_ARCHCC_FLAGS = -DARM_BIGLITTLE_TC2=1\r
+ GCC:*_*_ARM_PP_FLAGS = -DARM_BIGLITTLE_TC2=1\r
+!endif\r
+\r
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7\r
+\r
+ GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7\r
+ \r
+ XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag.common]\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE\r
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE\r
+ \r
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
+ # It could be set FALSE to save size.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+ \r
+[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"\r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress-CTA15-A7"\r
+\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|5\r
+\r
+ #\r
+ # NV Storage PCDs. Use base of 0x0C000000 for NOR1\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000\r
+\r
+ gArmTokenSpaceGuid.PcdVFPEnabled|1\r
+ \r
+ # Stacks for MPCores in Secure World\r
+ # SRAM (CS1) is only available between 0x14000000 and 0x14001000 on the model\r
+ # ZBT SRAM is available between 0x2E000000 and 0x2E010000 on the model\r
+!ifdef $(ARM_BIGLITTLE_TC2)\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x17000000\r
+!else\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E000000\r
+!endif\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x8000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000\r
+ # Share Monitor stacks with Secure World\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0\r
+ \r
+ # System Memory (1GB) - An additional 1GB will be added if UEFI is running on a 2GB Test Chip\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000\r
+\r
+!ifdef $(ARM_BIGLITTLE_TC2)\r
+ # TC2 Dual-Cluster profile\r
+ gArmPlatformTokenSpaceGuid.PcdClusterCount|2\r
+\r
+ # Core Ids and Gic values\r
+ # A15_0 = 0x000, GicCoreId = 0\r
+ # A15_1 = 0x001, GicCoreId = 1\r
+ # A7_0 = 0x100, GicCoreId = 2\r
+ # A7_1 = 0x101, GicCoreId = 3\r
+ # A7_2 = 0x102, GicCoreId = 4\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore|0x100\r
+ gArmTokenSpaceGuid.PcdGicPrimaryCoreId|2\r
+!endif\r
+ \r
+ #\r
+ # SEC Phase Global Variables :\r
+ # - 0x00-0x04: Debugger Exception Handler Pointer address \r
+ # - 0x04-0x08: Normal Exception Handler Pointer\r
+ # - 0x0C-0x10: MpSafe Serial Console SpinLock\r
+ # - 0x10-0x20: KfScb 8 Bakery Locks of 2Bytes each\r
+ # - 0x20-0x30: CCI 8 Bakery Locks of 2Bytes each\r
+ # - 0x30-0x48: ARM SMC Events (8 cores * 3 max_event * sizeof(UINT8))\r
+ gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x48\r
+ \r
+ #\r
+ # ARM PrimeCell\r
+ #\r
+\r
+ ## SP805 Watchdog - Motherboard Watchdog\r
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000\r
+ \r
+ ## PL011 - Serial Terminal\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C090000\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
+\r
+ ## PL031 RealTimeClock\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000\r
+\r
+!ifdef $(ARM_BIGLITTLE_TC2)\r
+ ## PL111 Lcd & HdLcd\r
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000\r
+ gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x2B000000\r
+ gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|5\r
+!endif\r
+\r
+ #\r
+ # PL180 MMC/SD card controller\r
+ #\r
+ gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048\r
+ gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000\r
+ \r
+ \r
+ #\r
+ # ARM PL390 General Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
+ \r
+ #\r
+ # ARM OS Loader\r
+ #\r
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: \r
+ gArmTokenSpaceGuid.PcdArmMachineType|2272\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0xE000000,0xE800000)"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400 earlyprintk debug verbose"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2\r
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0x0E800000,0x0E803000)"\r
+\r
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)\r
+ # PL111 - CLCD\r
+ #gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"\r
+ # HDLCD\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"\r
+\r
+ #\r
+ # ARM Architectural Timer Frequency\r
+ #\r
+!ifdef $(ARM_BIGLITTLE_TC2)\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|24000000\r
+!else\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|10000000\r
+!endif\r
+ \r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform\r
+#\r
+################################################################################\r
+[Components.common]\r
+ #\r
+ # PEI Phase modules\r
+ #\r
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {\r
+ <LibraryClasses>\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf\r
+ }\r
+\r
+ #\r
+ # DXE\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
+ }\r
+\r
+ #\r
+ # Architectural Protocols\r
+ #\r
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf \r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf \r
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+ #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
+ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf\r
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
+ \r
+ #\r
+ # Filesystems\r
+ #\r
+!ifndef $(ARM_BIGLITTLE_TC2)\r
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+!endif\r
+ \r
+ #\r
+ # Multimedia Card Interface\r
+ #\r
+ EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
+ ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
+ \r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ ArmPlatformPkg/Bds/Bds.inf\r
--- /dev/null
+#\r
+# Copyright (c) 2012, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+\r
+[FD.ARM_VEXPRESS_CTA15A7_EFI]\r
+BaseAddress = 0x81000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in remapped DRAM.\r
+Size = 0x000B0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device\r
+ErasePolarity = 1\r
+BlockSize = 0x00001000\r
+NumBlocks = 0xB0\r
+\r
+0x00000000|0x000B0000\r
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
+FV = FVMAIN_COMPACT\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.FvMain]\r
+BlockSize = 0x40\r
+NumBlocks = 0 # This FV gets compressed so make it just big enough\r
+FvAlignment = 8 # FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf \r
+\r
+ #\r
+ # PI DXE Drivers producing Architectural Protocols (EFI Services) \r
+ #\r
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+ \r
+ #\r
+ # Multiple Console IO support\r
+ #\r
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+ #INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
+ INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf\r
+ INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
+\r
+ #\r
+ # Multimedia Card Interface\r
+ #\r
+ INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
+ INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
+ \r
+ #\r
+ # Filesystems\r
+ #\r
+!ifndef $(ARM_BIGLITTLE_TC2)\r
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+!endif\r
+ \r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+ \r
+ #\r
+ # UEFI application\r
+ # \r
+ INF ShellBinPkg/UefiShell/UefiShell.inf\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ INF ArmPlatformPkg/Bds/Bds.inf\r
+\r
+[FV.FVMAIN_COMPACT]\r
+FvBaseAddress = 0x81000000\r
+FvForceRebase = TRUE\r
+FvAlignment = 8\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf\r
+ \r
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
+ SECTION FV_IMAGE = FVMAIN\r
+ }\r
+ }\r
+\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+\r
+############################################################################\r
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # \r
+############################################################################\r
+#\r
+#[Rule.Common.DXE_DRIVER]\r
+# FILE DRIVER = $(NAMED_GUID) {\r
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+# COMPRESS PI_STD {\r
+# GUIDED {\r
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+# UI STRING="$(MODULE_NAME)" Optional\r
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+# }\r
+# }\r
+# }\r
+#\r
+############################################################################\r
+\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING ="$(MODULE_NAME)" Optional \r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional \r
+ }\r
+\r
+[Rule.Common.PEIM.TIANOCOMPRESSED]\r
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ UI STRING ="$(MODULE_NAME)" Optional \r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER.BINARY]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION.BINARY]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
#\r
gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode|3|UINT32|0x00000003\r
gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000004\r
+ gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000009\r
--- /dev/null
+/** @file\r
+* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
+*\r
+* Copyright (c) 2012, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __ARM_VEXPRESS_CTA15A7_H__\r
+#define __ARM_VEXPRESS_CTA15A7_H__\r
+\r
+#include <VExpressMotherBoard.h>\r
+\r
+/***********************************************************************************\r
+// Platform Memory Map\r
+************************************************************************************/\r
+\r
+// Motherboard Peripheral and On-chip peripheral\r
+#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000\r
+\r
+#ifdef ARM_BIGLITTLE_TC2\r
+\r
+// Secure NOR Flash\r
+#define ARM_VE_SEC_NOR0_BASE 0x00000000\r
+#define ARM_VE_SEC_NOR0_SZ SIZE_64MB\r
+\r
+// Secure RAM\r
+#define ARM_VE_SEC_RAM0_BASE 0x04000000\r
+#define ARM_VE_SEC_RAM0_SZ SIZE_64MB\r
+\r
+#endif\r
+\r
+// NOR Flash 0\r
+#define ARM_VE_SMB_NOR0_BASE 0x08000000\r
+#define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r
+// NOR Flash 1\r
+#define ARM_VE_SMB_NOR1_BASE 0x0C000000\r
+#define ARM_VE_SMB_NOR1_SZ SIZE_64MB\r
+\r
+// SRAM\r
+#define ARM_VE_SMB_SRAM_BASE 0x14000000\r
+#define ARM_VE_SMB_SRAM_SZ SIZE_32MB\r
+\r
+// USB, Ethernet, VRAM\r
+#ifdef ARM_BIGLITTLE_TC2\r
+#define ARM_VE_SMB_PERIPH_BASE 0x18000000\r
+#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_32MB + SIZE_16MB)\r
+#else\r
+#define ARM_VE_SMB_PERIPH_BASE 0x1C000000\r
+#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_16MB)\r
+#endif\r
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE\r
+\r
+// On-Chip non-secure ROM\r
+#ifdef ARM_BIGLITTLE_TC2\r
+#define ARM_VE_TC2_NON_SECURE_ROM_BASE 0x1F000000\r
+#define ARM_VE_TC2_NON_SECURE_ROM_SZ SIZE_16MB\r
+#endif\r
+\r
+// On-Chip Peripherals\r
+#define ARM_VE_ONCHIP_PERIPH_BASE 0x20000000\r
+#define ARM_VE_ONCHIP_PERIPH_SZ 0x10000000\r
+\r
+// On-Chip non-secure SRAM\r
+#ifdef ARM_BIGLITTLE_TC2\r
+#define ARM_VE_TC2_NON_SECURE_SRAM_BASE 0x2E000000\r
+#define ARM_VE_TC2_NON_SECURE_SRAM_SZ SIZE_64KB\r
+#endif\r
+\r
+// Allocate a section for the VRAM (Video RAM)\r
+// If 0 then allow random memory allocation\r
+#define LCD_VRAM_CORE_TILE_BASE 0\r
+\r
+// Define SEC phase sync point\r
+#define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE (ARM_SEC_EVENT_MAX + 1)\r
+\r
+/***********************************************************************************\r
+ Core Tile memory-mapped Peripherals\r
+************************************************************************************/\r
+\r
+// PL354 Static Memory Controller Base\r
+#ifdef ARM_BIGLITTLE_TC2\r
+#define ARM_VE_SMC_CTRL_BASE 0x7FFD0000\r
+#else\r
+#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)\r
+#endif\r
+\r
+#define ARM_CTA15A7_SCC_BASE 0x7FFF0000\r
+#define ARM_CTA15A7_SCC_CFGREG48 (ARM_CTA15A7_SCC_BASE + 0x700)\r
+\r
+#define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48\r
+\r
+#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >> 20) & 0xF)\r
+#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >> 16) & 0xF)\r
+#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0)\r
+#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1)\r
+\r
+#define ARM_CTA15A7_SPC_BASE 0x7FFF0B00\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + 0x24)\r
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT (ARM_CTA15A7_SPC_BASE + 0x3C)\r
+#define ARM_CTA15A7_SPC_A15_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x68)\r
+#define ARM_CTA15A7_SPC_A15_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x6C)\r
+#define ARM_CTA15A7_SPC_A15_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x70)\r
+#define ARM_CTA15A7_SPC_A15_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x74)\r
+#define ARM_CTA15A7_SPC_A7_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x78)\r
+#define ARM_CTA15A7_SPC_A7_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x7C)\r
+#define ARM_CTA15A7_SPC_A7_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x80)\r
+#define ARM_CTA15A7_SPC_A7_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x84)\r
+\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0 (1 << 0)\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1 (1 << 1)\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0 (1 << 2)\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1 (1 << 3)\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0 (1 << 4)\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1 (1 << 5)\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2 (1 << 6)\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0 (1 << 7)\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1 (1 << 8)\r
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2 (1 << 9)\r
+\r
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0 (1 << 0)\r
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1 (1 << 1)\r
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2 (1 << 2)\r
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0 (1 << 3)\r
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1 (1 << 4)\r
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2 (1 << 5)\r
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2 (1 << 6)\r
+\r
+\r
+/***********************************************************************************\r
+// Memory-mapped peripherals\r
+************************************************************************************/\r
+\r
+/*// SP810 Controller\r
+#undef SP810_CTRL_BASE\r
+#define SP810_CTRL_BASE 0x1C020000\r
+\r
+// PL111 Colour LCD Controller\r
+#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE\r
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1\r
+#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1\r
+\r
+// VRAM offset for the PL111 Colour LCD Controller on the motherboard\r
+#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)*/\r
+\r
+#endif\r
--- /dev/null
+#/* @file\r
+#\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = CTA15A7ArmVExpressLib\r
+ FILE_GUID = b98a6cb7-d472-4128-ad62-a7347f85ce13\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmPlatformLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ ArmLib\r
+ MemoryAllocationLib\r
+ SerialPortLib\r
+\r
+[Sources.common]\r
+ CTA15-A7.c\r
+ CTA15-A7Mem.c\r
+ CTA15-A7Helper.asm | RVCT\r
+ CTA15-A7Helper.S | GCC\r
+\r
+[FeaturePcd]\r
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\r
+ gArmPlatformTokenSpaceGuid.PcdStandalone\r
+\r
+[FixedPcd]\r
+ gArmPlatformTokenSpaceGuid.PcdCoreCount\r
+\r
+ gArmTokenSpaceGuid.PcdTrustzoneSupport\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize\r
+ gArmTokenSpaceGuid.PcdFvBaseAddress\r
+\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2012, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
+\r
+#include <ArmPlatform.h>\r
+\r
+ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] = {\r
+ {\r
+ // Cluster 0, Core 0\r
+ 0x0, 0x0,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r
+ (UINT64)0\r
+ },\r
+ {\r
+ // Cluster 0, Core 1\r
+ 0x0, 0x1,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r
+ (UINT64)0\r
+ },\r
+#ifndef ARM_BIGLITTLE_TC2\r
+ {\r
+ // Cluster 0, Core 2\r
+ 0x0, 0x2,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r
+ (UINT64)0\r
+ },\r
+ {\r
+ // Cluster 0, Core 3\r
+ 0x0, 0x3,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r
+ (UINT64)0\r
+ },\r
+#endif\r
+ {\r
+ // Cluster 1, Core 0\r
+ 0x1, 0x0,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r
+ (UINT64)0\r
+ },\r
+ {\r
+ // Cluster 1, Core 1\r
+ 0x1, 0x1,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r
+ (UINT64)0\r
+ },\r
+ {\r
+ // Cluster 1, Core 2\r
+ 0x1, 0x2,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r
+ (UINT64)0\r
+ }\r
+#ifndef ARM_BIGLITTLE_TC2\r
+ ,{\r
+ // Cluster 1, Core 3\r
+ 0x1, 0x3,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r
+ (UINT64)0\r
+ }\r
+#endif\r
+};\r
+\r
+/**\r
+ Return the current Boot Mode\r
+\r
+ This function returns the boot reason on the platform\r
+\r
+ @return Return the current Boot Mode of the platform\r
+\r
+**/\r
+EFI_BOOT_MODE\r
+ArmPlatformGetBootMode (\r
+ VOID\r
+ )\r
+{\r
+ return BOOT_WITH_FULL_CONFIGURATION;\r
+}\r
+\r
+/**\r
+ Initialize controllers that must setup in the normal world\r
+\r
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim\r
+ in the PEI phase.\r
+\r
+**/\r
+RETURN_STATUS\r
+ArmPlatformInitialize (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ if (!IS_PRIMARY_CORE(MpId)) {\r
+ return RETURN_SUCCESS;\r
+ }\r
+\r
+ // Nothing to do here\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Initialize the system (or sometimes called permanent) memory\r
+\r
+ This memory is generally represented by the DRAM.\r
+\r
+**/\r
+VOID\r
+ArmPlatformInitializeSystemMemory (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+EFI_STATUS\r
+PrePeiCoreGetMpCoreInfo (\r
+ OUT UINTN *CoreCount,\r
+ OUT ARM_CORE_INFO **ArmCoreTable\r
+ )\r
+{\r
+ // Only support one cluster\r
+ *CoreCount = sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM_CORE_INFO);\r
+ *ArmCoreTable = mVersatileExpressCTA15A7InfoTable;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore\r
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;\r
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
+\r
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+ &mArmMpCoreInfoPpiGuid,\r
+ &mMpCoreInfoPpi\r
+ }\r
+};\r
+\r
+VOID\r
+ArmPlatformGetPlatformPpiList (\r
+ OUT UINTN *PpiListSize,\r
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
+ )\r
+{\r
+ *PpiListSize = sizeof(gPlatformPpiTable);\r
+ *PpiList = gPlatformPpiTable;\r
+}\r
--- /dev/null
+//\r
+// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <Library/ArmLib.h>\r
+\r
+.text \r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and r1, r0, #ARM_CORE_MASK\r
+ and r0, r0, #ARM_CLUSTER_MASK\r
+ add r0, r1, r0, LSR #7\r
+ bx lr\r
+\r
--- /dev/null
+//\r
+// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <Library/ArmLib.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformGetCorePosition\r
+\r
+ PRESERVE8\r
+ AREA CTA15A7Helper, CODE, READONLY\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformGetCorePosition FUNCTION\r
+ and r1, r0, #ARM_CORE_MASK\r
+ and r0, r0, #ARM_CLUSTER_MASK\r
+ add r0, r1, r0, LSR #7\r
+ bx lr\r
+ ENDFUNC\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2012, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <ArmPlatform.h>\r
+\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+\r
+/**\r
+ Return the Virtual Memory Map of your platform\r
+\r
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
+\r
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
+ Virtual Memory mapping. This array must be ended by a zero-filled\r
+ entry\r
+\r
+**/\r
+VOID\r
+ArmPlatformGetVirtualMemoryMap (\r
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
+ )\r
+{\r
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
+ UINTN Index = 0;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+\r
+ ASSERT (VirtualMemoryMap != NULL);\r
+\r
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
+ if (VirtualMemoryTable == NULL) {\r
+ return;\r
+ }\r
+\r
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
+ } else {\r
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
+ }\r
+\r
+ // Detect if it is a 1GB or 2GB Test Chip\r
+ // [16:19]: 0=1GB TC2, 1=2GB TC2\r
+ if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {\r
+ DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+ PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),\r
+ 0x40000000\r
+ );\r
+ }\r
+\r
+#ifdef ARM_BIGLITTLE_TC2\r
+ // Secure NOR0 Flash\r
+ VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_NOR0_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SEC_NOR0_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+ // Secure RAM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SEC_RAM0_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_RAM0_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SEC_RAM0_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+#endif\r
+\r
+ // SMB CS0 - NOR0 Flash\r
+ VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
+ VirtualMemoryTable[Index].Length = SIZE_256KB * 255;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+ // Environment Variables region\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
+ VirtualMemoryTable[Index].Length = SIZE_64KB * 4;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // SMB CS1 or CS4 - NOR1 Flash\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE;\r
+ VirtualMemoryTable[Index].Length = SIZE_256KB * 255;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+ // Environment Variables region\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);\r
+ VirtualMemoryTable[Index].Length = SIZE_64KB * 4;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // SMB CS3 or CS1 - PSRAM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // Motherboard peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+#ifdef ARM_BIGLITTLE_TC2\r
+ // Non-secure ROM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_ROM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+#endif\r
+\r
+ // OnChip peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ONCHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_ONCHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_ONCHIP_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+ // SCC Region\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_CTA15A7_SCC_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_CTA15A7_SCC_BASE;\r
+ VirtualMemoryTable[Index].Length = SIZE_64KB;\r
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+\r
+#ifdef ARM_BIGLITTLE_TC2\r
+ // TC2 OnChip non-secure SRAM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_SRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+#endif\r
+\r
+#ifndef ARM_BIGLITTLE_TC2\r
+ // Workaround for SRAM bug in RTSM\r
+ if (PcdGet32 (PcdSystemMemoryBase) != 0x80000000) {\r
+ VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;\r
+ VirtualMemoryTable[Index].VirtualBase = 0x80000000;\r
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemoryBase) - 0x80000000;\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+ }\r
+#endif\r
+\r
+ // DDR\r
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemorySize);\r
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
+\r
+ // End of Table\r
+ VirtualMemoryTable[++Index].PhysicalBase = 0;\r
+ VirtualMemoryTable[Index].VirtualBase = 0;\r
+ VirtualMemoryTable[Index].Length = 0;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
+ ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
+}\r
+\r
+/**\r
+ Return the EFI Memory Map provided by extension memory on your platform\r
+\r
+ This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource\r
+ Descriptor HOBs used by DXE core.\r
+\r
+ @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an\r
+ EFI Memory region. This array must be ended by a zero-filled entry\r
+\r
+**/\r
+EFI_STATUS\r
+ArmPlatformGetAdditionalSystemMemory (\r
+ OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
--- /dev/null
+/**\r
+\r
+ Copyright (c) 2012, ARM Ltd. All rights reserved.\r
+ \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/ArmPlatformSysConfigLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/LcdPlatformLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+\r
+#include <Protocol/Cpu.h>\r
+#include <Protocol/EdidDiscovered.h>\r
+#include <Protocol/EdidActive.h>\r
+\r
+#include <ArmPlatform.h>\r
+\r
+typedef struct {\r
+ UINT32 Mode;\r
+ UINT32 HorizontalResolution;\r
+ UINT32 VerticalResolution;\r
+ LCD_BPP Bpp;\r
+ UINT32 OscFreq;\r
+\r
+ // These are used by HDLCD\r
+ UINT32 HSync;\r
+ UINT32 HBackPorch;\r
+ UINT32 HFrontPorch;\r
+ UINT32 VSync;\r
+ UINT32 VBackPorch;\r
+ UINT32 VFrontPorch;\r
+} LCD_RESOLUTION;\r
+\r
+\r
+LCD_RESOLUTION mResolutions[] = {\r
+ { // Mode 0 : VGA : 640 x 480 x 24 bpp\r
+ VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,\r
+ VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
+ VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
+ },\r
+ { // Mode 1 : SVGA : 800 x 600 x 24 bpp\r
+ SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,\r
+ SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
+ SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
+ },\r
+ { // Mode 2 : XGA : 1024 x 768 x 24 bpp\r
+ XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,\r
+ XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
+ XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
+ },\r
+ { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp\r
+ SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),\r
+ SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,\r
+ SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH\r
+ },\r
+ { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp\r
+ UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),\r
+ UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,\r
+ UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH\r
+ },\r
+ { // Mode 5 : HD : 1920 x 1080 x 24 bpp\r
+ HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),\r
+ HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,\r
+ HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH\r
+ }\r
+};\r
+\r
+EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {\r
+ 0,\r
+ NULL\r
+};\r
+\r
+EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {\r
+ 0,\r
+ NULL\r
+};\r
+\r
+EFI_STATUS\r
+LcdPlatformInitializeDisplay (\r
+ IN EFI_HANDLE Handle\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ // Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard\r
+ Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);\r
+ if (EFI_ERROR(Status)) {\r
+ return Status;\r
+ }\r
+\r
+ // Install the EDID Protocols\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &Handle,\r
+ &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,\r
+ &gEfiEdidActiveProtocolGuid, &mEdidActive,\r
+ NULL\r
+ );\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformGetVram (\r
+ OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,\r
+ OUT UINTN* VramSize\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_CPU_ARCH_PROTOCOL *Cpu;\r
+ EFI_ALLOCATE_TYPE AllocationType;\r
+\r
+ // Set the vram size\r
+ *VramSize = LCD_VRAM_SIZE;\r
+\r
+ *VramBaseAddress = (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE;\r
+\r
+ // Allocate the VRAM from the DRAM so that nobody else uses it.\r
+ if (*VramBaseAddress == 0) {\r
+ AllocationType = AllocateAnyPages;\r
+ } else {\r
+ AllocationType = AllocateAddress;\r
+ }\r
+ Status = gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);\r
+ if (EFI_ERROR(Status)) {\r
+ return Status;\r
+ }\r
+\r
+ // Ensure the Cpu architectural protocol is already installed\r
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable.\r
+ Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);\r
+ ASSERT_EFI_ERROR(Status);\r
+ if (EFI_ERROR(Status)) {\r
+ gBS->FreePool (VramBaseAddress);\r
+ return Status;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+UINT32\r
+LcdPlatformGetMaxMode (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // The following line will report correctly the total number of graphics modes\r
+ // that could be supported by the graphics driver:\r
+ //\r
+ return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION));\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformSetMode (\r
+ IN UINT32 ModeNumber\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ // Set the video mode oscillator\r
+ do {\r
+ Status = ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq);\r
+ } while (Status == EFI_TIMEOUT);\r
+ if (EFI_ERROR(Status)) {\r
+ ASSERT_EFI_ERROR (Status);\r
+ return Status;\r
+ }\r
+\r
+ // Set the DVI into the new mode\r
+ do {\r
+ Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);\r
+ } while (Status == EFI_TIMEOUT);\r
+ if (EFI_ERROR(Status)) {\r
+ ASSERT_EFI_ERROR (Status);\r
+ return Status;\r
+ }\r
+\r
+ // Set the multiplexer\r
+ Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);\r
+ if (EFI_ERROR(Status)) {\r
+ ASSERT_EFI_ERROR (Status);\r
+ return Status;\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformQueryMode (\r
+ IN UINT32 ModeNumber,\r
+ OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info\r
+ )\r
+{\r
+ if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Info->Version = 0;\r
+ Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;\r
+ Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;\r
+ Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;\r
+\r
+ switch (mResolutions[ModeNumber].Bpp) {\r
+ case LCD_BITS_PER_PIXEL_24:\r
+ Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;\r
+ Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;\r
+ Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;\r
+ Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;\r
+ Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;\r
+ break;\r
+\r
+ case LCD_BITS_PER_PIXEL_16_555:\r
+ case LCD_BITS_PER_PIXEL_16_565:\r
+ case LCD_BITS_PER_PIXEL_12_444:\r
+ case LCD_BITS_PER_PIXEL_8:\r
+ case LCD_BITS_PER_PIXEL_4:\r
+ case LCD_BITS_PER_PIXEL_2:\r
+ case LCD_BITS_PER_PIXEL_1:\r
+ default:\r
+ // These are not supported\r
+ ASSERT(FALSE);\r
+ break;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformGetTimings (\r
+ IN UINT32 ModeNumber,\r
+ OUT UINT32* HRes,\r
+ OUT UINT32* HSync,\r
+ OUT UINT32* HBackPorch,\r
+ OUT UINT32* HFrontPorch,\r
+ OUT UINT32* VRes,\r
+ OUT UINT32* VSync,\r
+ OUT UINT32* VBackPorch,\r
+ OUT UINT32* VFrontPorch\r
+ )\r
+{\r
+ if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *HRes = mResolutions[ModeNumber].HorizontalResolution;\r
+ *HSync = mResolutions[ModeNumber].HSync;\r
+ *HBackPorch = mResolutions[ModeNumber].HBackPorch;\r
+ *HFrontPorch = mResolutions[ModeNumber].HFrontPorch;\r
+ *VRes = mResolutions[ModeNumber].VerticalResolution;\r
+ *VSync = mResolutions[ModeNumber].VSync;\r
+ *VBackPorch = mResolutions[ModeNumber].VBackPorch;\r
+ *VFrontPorch = mResolutions[ModeNumber].VFrontPorch;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformGetBpp (\r
+ IN UINT32 ModeNumber,\r
+ OUT LCD_BPP * Bpp\r
+ )\r
+{\r
+ if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *Bpp = mResolutions[ModeNumber].Bpp;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+#/** @file\r
+# \r
+# Component description file for HdLcdArmLib module\r
+# \r
+# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = HdLcdArmVExpress\r
+ FILE_GUID = 535a720e-06c0-4bb9-b563-452216abbed4\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = LcdPlatformLib\r
+ \r
+[Sources.common]\r
+ \r
+HdLcdArmVExpress.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec\r
+ \r
+[LibraryClasses]\r
+ BaseLib\r
+ ArmPlatformSysConfigLib\r
+\r
+[Protocols]\r
+ gEfiEdidDiscoveredProtocolGuid # Produced\r
+ gEfiEdidActiveProtocolGuid # Produced\r
+\r
+[Pcd]\r
+ gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode\r
+ gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId
\ No newline at end of file
projects / mirror_edk2.git / commitdiff