UefiCpuPkg/PiSmmCpu: Remove hardcode 48 address size limitation

5-level paging can be enabled on CPU which supports up to 52 physical
address size. But when the feature was enabled, the 48 address size
limit was not removed and the 5-level paging testing didn't access
address >= 2^48. So the issue wasn't detected until recently an
address >= 2^48 is accessed.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index fd6583f9d172aa2846c2c8f97f59a857110bd6f2..89143810b642294110d7ba00873509a2d1ef04ae 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -1887,11 +1887,13 @@ InitializeMpServiceData (
   IN UINTN       ShadowStackSize\r
   )\r
 {\r
-  UINT32                    Cr3;\r
-  UINTN                     Index;\r
-  UINT8                     *GdtTssTables;\r
-  UINTN                     GdtTableStepSize;\r
-  CPUID_VERSION_INFO_EDX    RegEdx;\r
+  UINT32                          Cr3;\r
+  UINTN                           Index;\r
+  UINT8                           *GdtTssTables;\r
+  UINTN                           GdtTableStepSize;\r
+  CPUID_VERSION_INFO_EDX          RegEdx;\r
+  UINT32                          MaxExtendedFunction;\r
+  CPUID_VIR_PHY_ADDRESS_SIZE_EAX  VirPhyAddressSize;\r
 \r
   //\r
   // Determine if this CPU supports machine check\r
@@ -1918,9 +1920,17 @@ InitializeMpServiceData (
   // Initialize physical address mask\r
   // NOTE: Physical memory above virtual address limit is not supported !!!\r
   //\r
-  AsmCpuid (0x80000008, (UINT32*)&Index, NULL, NULL, NULL);\r
-  gPhyMask = LShiftU64 (1, (UINT8)Index) - 1;\r
-  gPhyMask &= (1ull << 48) - EFI_PAGE_SIZE;\r
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);\r
+  if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
+    AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);\r
+  } else {\r
+    VirPhyAddressSize.Bits.PhysicalAddressBits = 36;\r
+  }\r
+  gPhyMask  = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;\r
+  //\r
+  // Clear the low 12 bits\r
+  //\r
+  gPhyMask &= 0xfffffffffffff000ULL;\r
 \r
   //\r
   // Create page tables\r