OvmfPkg/PlatformInitLib: q35 mtrr setup fix

Traditional q35 memory layout is 2.75 GB of low memory, leaving room
for the pcie mmconfig at 0xb0000000 and the 32-bit pci mmio window at
0xc0000000.  Because of that OVMF tags the memory range above
0xb0000000 as uncachable via mtrr.

A while ago qemu started to gigabyte-align memory by default (to make
huge pages more effective) and q35 uses only 2G of low memory in that
case.  Which effectively makes the 32-bit pci mmio window start at
0x80000000.

This patch updates the mtrr setup code accordingly.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>

diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
index 942eaf89cfcf02c1018c1dfb49f9dcc5fdc48807..d1a4f4b207911f06f5f5e962c4ea4724cef838c0 100644 (file)
--- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
+++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
@@ -55,15 +55,25 @@ PlatformQemuUc32BaseInitialization (
   }\r
 \r
   if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
-    //\r
-    // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,\r
-    // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for\r
-    // setting PcdPciExpressBaseAddress such that describing the\r
-    // [PcdPciExpressBaseAddress, 4GB) range require a very small number of\r
-    // variable MTRRs (preferably 1 or 2).\r
-    //\r
+    LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
     ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);\r
-    PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress);\r
+    ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >= LowerMemorySize);\r
+\r
+    if (LowerMemorySize <= BASE_2GB) {\r
+      // Newer qemu with gigabyte aligned memory,\r
+      // 32-bit pci mmio window is 2G -> 4G then.\r
+      PlatformInfoHob->Uc32Base = BASE_2GB;\r
+    } else {\r
+      //\r
+      // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,\r
+      // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for\r
+      // setting PcdPciExpressBaseAddress such that describing the\r
+      // [PcdPciExpressBaseAddress, 4GB) range require a very small number of\r
+      // variable MTRRs (preferably 1 or 2).\r
+      //\r
+      PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress);\r
+    }\r
+\r
     return;\r
   }\r
 \r