ArmPkg/AArch64Mmu: use architecturally correct definitions for XN/UXN

The non-privileged execute never (UXN) page table bit defined for the
EL1&0 translation regime and the execute never (XN) bit defined for the
EL2 and EL3 translation regimes happen to share the same bit position,
but they are in fact defined distinctly by the architecture. So define
both bits explicitly, and add comments in places where we take advantage
of the fact that they share the same bit position.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18585 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 2398ba2539c79ac74eb2b255683059b5fb2b4bfe..22e492d61dc04489b63c7e3685efa3e4fe662946 100644 (file)
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -75,12 +75,14 @@
 #define TT_AF                                   BIT10\r
 \r
 #define TT_PXN_MASK                             BIT53\r
-#define TT_UXN_MASK                             BIT54\r
+#define TT_UXN_MASK                             BIT54   // EL1&0\r
+#define TT_XN_MASK                              BIT54   // EL2 / EL3\r
 \r
 #define TT_ATTRIBUTES_MASK                      ((0xFFFULL << 52) | (0x3FFULL << 2))\r
 \r
 #define TT_TABLE_PXN                            BIT59\r
-#define TT_TABLE_XN                             BIT60\r
+#define TT_TABLE_UXN                            BIT60   // EL1&0\r
+#define TT_TABLE_XN                             BIT60   // EL2 / EL3\r
 #define TT_TABLE_NS                             BIT63\r
 \r
 #define TT_TABLE_AP_MASK                        (BIT62 | BIT61)\r

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index 3765d61ccd487dc84fbb15ed7fccce58e36c8666..d82c82c202316c2a51623711f728f35aa04ed29f 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -335,7 +335,8 @@ GetBlockEntryListFromAddress (
         if (Attributes & TT_PXN_MASK) {\r
           TableAttributes = TT_TABLE_PXN;\r
         }\r
-        if (Attributes & TT_UXN_MASK) {\r
+        // XN maps to UXN in the EL1&0 translation regime\r
+        if (Attributes & TT_XN_MASK) {\r
           TableAttributes = TT_TABLE_XN;\r
         }\r
         if (Attributes & TT_NS) {\r