Ia32/ARShiftU64.c | MSFT \r
Ia32/Thunk16.nasm | MSFT\r
Ia32/Thunk16.asm | MSFT\r
+ Ia32/EnablePaging64.nasm| MSFT\r
Ia32/EnablePaging64.asm | MSFT\r
Ia32/EnableCache.c | MSFT\r
Ia32/DisableCache.c | MSFT\r
Ia32/ARShiftU64.asm | INTEL \r
Ia32/Thunk16.nasm | INTEL\r
Ia32/Thunk16.asm | INTEL\r
+ Ia32/EnablePaging64.nasm| INTEL\r
Ia32/EnablePaging64.asm | INTEL\r
Ia32/EnableCache.asm | INTEL\r
Ia32/DisableCache.asm | INTEL\r
Ia32/Thunk16.nasm | GCC \r
Ia32/Thunk16.S | XCODE \r
Ia32/EnableDisableInterrupts.S | GCC \r
+ Ia32/EnablePaging64.nasm| GCC\r
Ia32/EnablePaging64.S | GCC \r
Ia32/DisablePaging32.S | GCC \r
Ia32/EnablePaging32.S | GCC \r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; EnablePaging64.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmEnablePaging64 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; InternalX86EnablePaging64 (\r
+; IN UINT16 Cs,\r
+; IN UINT64 EntryPoint,\r
+; IN UINT64 Context1, OPTIONAL\r
+; IN UINT64 Context2, OPTIONAL\r
+; IN UINT64 NewStack\r
+; );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(InternalX86EnablePaging64)\r
+ASM_PFX(InternalX86EnablePaging64):\r
+ cli\r
+ mov DWORD [esp], .0 ; offset for far retf, seg is the 1st arg\r
+ mov eax, cr4\r
+ or al, (1 << 5)\r
+ mov cr4, eax ; enable PAE\r
+ mov ecx, 0xc0000080\r
+ rdmsr\r
+ or ah, 1 ; set LME\r
+ wrmsr\r
+ mov eax, cr0\r
+ bts eax, 31 ; set PG\r
+ mov cr0, eax ; enable paging\r
+ retf ; topmost 2 dwords hold the address\r
+.0:\r
+ DB 0x67, 0x48 ; 32-bit address size, 64-bit operand size\r
+ mov ebx, [esp] ; mov rbx, [esp]\r
+ DB 0x67, 0x48\r
+ mov ecx, [esp + 8] ; mov rcx, [esp + 8]\r
+ DB 0x67, 0x48\r
+ mov edx, [esp + 0x10] ; mov rdx, [esp + 10h]\r
+ DB 0x67, 0x48\r
+ mov esp, [esp + 0x18] ; mov rsp, [esp + 18h]\r
+ DB 0x48\r
+ add esp, -0x20 ; add rsp, -20h\r
+ call ebx ; call rbx\r
+ hlt ; no one should get here\r
+\r