CPUID Hybrid Information Enumeration Leaf\r
\r
@param EAX CPUID_HYBRID_INFORMATION (0x1A)\r
- @param ECX CPUID_HYBRID_INFORMATION_SUB_LEAF (0x00).\r
+ @param ECX CPUID_HYBRID_INFORMATION_MAIN_LEAF (0x00).\r
\r
@retval EAX Enumerates the native model ID and core type described\r
by the type CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX\r
\r
AsmCpuidEx (\r
CPUID_HYBRID_INFORMATION,\r
- CPUID_HYBRID_INFORMATION_SUB_LEAF,\r
+ CPUID_HYBRID_INFORMATION_MAIN_LEAF,\r
&Eax, NULL, NULL, NULL\r
);\r
@endcode\r
#define CPUID_HYBRID_INFORMATION 0x1A\r
\r
///\r
-/// CPUID Hybrid Information Enumeration sub-leaf\r
+/// CPUID Hybrid Information Enumeration main leaf\r
///\r
-#define CPUID_HYBRID_INFORMATION_SUB_LEAF 0x00\r
+#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00\r
\r
/**\r
CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION,\r
- sub-leaf #CPUID_HYBRID_INFORMATION_SUB_LEAF.\r
+ main leaf #CPUID_HYBRID_INFORMATION_MAIN_LEAF.\r
**/\r
typedef union {\r
///\r
UINT32 Uint32;\r
} CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX;\r
\r
+///\r
+/// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType\r
+///\r
+#define CPUID_CORE_TYPE_INTEL_ATOM 0x20\r
+#define CPUID_CORE_TYPE_INTEL_CORE 0x40\r
+///\r
+/// @}\r
+///\r
+\r
\r
/**\r
CPUID V2 Extended Topology Enumeration Leaf\r
//\r
Context->ProcessorInfo[ProcessorIndex].CoreType = 0;\r
if (CpuidMaxInput >= CPUID_HYBRID_INFORMATION) {\r
- AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_SUB_LEAF, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL);\r
+ AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_MAIN_LEAF, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL);\r
Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8) NativeModelIdAndCoreTypeEax.Bits.CoreType;\r
}\r
\r