OvmfPkg: PlatformBdsLib: Platform dependent PCI/IRQ initialization

Merge PciInitialization() and AcpiInitialization() into a single
function, PciAcpiInitialization(), and use a PCD set during PEI to
detect the underlying platform type (PIIX4 or Q35/MCH) and therefore
the addresses of the registers to be initialized.

Add LNK[A-H] routing target initialization for the Q35 platform.

Additionally, initialize PCI_INTERRUPT_LINE registers for the typical
set of PCI devices included by QEMU with the Q35 machine type. The
corresponding PIIX4 initialization of PCI_INTERRUPT_LINE registers is
cleaned up and the list of PIIX4 PCI devices updated to the list
typically included with QEMU.

NOTE: The list of PCI devices for which we initialize PCI_INTERRUPT_LINE
is hard-coded, and, depending on how QEMU devices are configured on
the command line, may miss some devices, or (harmlessly) attempt to
initialize devices which are not present in the system. A subsequent
patch will replace this hard-coded list with a mechanism to correctly
initialize PCI_INTERRUPT_LINE for applicable present PCI devices only.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16379 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
index 4b76c6e89030b05c1df36dbcba9ce122a2e2ab85..6fc5a8978021821b281cc9ec74978f7388f56fc6 100644 (file)
--- a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -717,63 +717,92 @@ Returns:
 \r
 \r
 VOID\r
-PciInitialization (\r
+PciAcpiInitialization (\r
   )\r
 {\r
-  //\r
-  // Bus 0, Device 0, Function 0 - Host to PCI Bridge\r
-  //\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 0, 0, 0x3c), 0x00);\r
-\r
-  //\r
-  // Bus 0, Device 1, Function 0 - PCI to ISA Bridge\r
-  //\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x3c), 0x00);\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x60), 0x0b); // LNKA routing target\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x61), 0x0b); // LNKB routing target\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x62), 0x0a); // LNKC routing target\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x63), 0x0a); // LNKD routing target\r
-\r
-  //\r
-  // Bus 0, Device 1, Function 1 - IDE Controller\r
-  //\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 1, 1, 0x3c), 0x00);\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 1, 1, 0x0d), 0x40);\r
+  UINT16 HostBridgeDevId;\r
+  UINTN  Pmba;\r
 \r
   //\r
-  // Bus 0, Device 1, Function 3 - Power Managment Controller\r
+  // Query Host Bridge DID to determine platform type\r
   //\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 1, 3, 0x3c), 0x09);\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 1, 3, 0x3d), 0x01); // INTA\r
-\r
-  //\r
-  // Bus 0, Device 2, Function 0 - Video Controller\r
-  //\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 2, 0, 0x3c), 0x00);\r
+  HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
+  switch (HostBridgeDevId) {\r
+    case INTEL_82441_DEVICE_ID:\r
+      Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      //\r
+      // 00:01.0 ISA Bridge (PIIX4) LNK routing targets\r
+      //\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x60), 0x0b); // A\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x61), 0x0b); // B\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x62), 0x0a); // C\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x63), 0x0a); // D\r
+      break;\r
+    case INTEL_Q35_MCH_DEVICE_ID:\r
+      Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
+      //\r
+      // 00:1f.0 LPC Bridge (Q35) LNK routing targets\r
+      //\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x60), 0x0a); // A\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x61), 0x0a); // B\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x62), 0x0b); // C\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x63), 0x0b); // D\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x68), 0x0a); // E\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x69), 0x0a); // F\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6a), 0x0b); // G\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), 0x0b); // H\r
+      break;\r
+    default:\r
+      DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+        __FUNCTION__, HostBridgeDevId));\r
+      ASSERT (FALSE);\r
+      return;\r
+  }\r
 \r
   //\r
-  // Bus 0, Device 3, Function 0 - Network Controller\r
+  // Set ACPI SCI_EN bit in PMCNTRL\r
   //\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 3, 0, 0x3c), 0x0a);\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 3, 0, 0x3d), 0x01); // INTA (-> LNKC)\r
+  IoOr16 ((PciRead32 (Pmba) & ~BIT0) + 4, BIT0);\r
 \r
   //\r
-  // Bus 0, Device 5, Function 0 - RAM Memory\r
+  // Initialize PCI_INTERRUPT_LINE for commonly encountered devices and slots\r
   //\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 5, 0, 0x3c), 0x0b);\r
-  PciWrite8 (PCI_LIB_ADDRESS (0, 5, 0, 0x3d), 0x01); // INTA (-> LNKA)\r
-}\r
-\r
-\r
-VOID\r
-AcpiInitialization (\r
-  VOID\r
-  )\r
-{\r
-  //\r
-  // Set ACPI SCI_EN bit in PMCNTRL\r
+  // FIXME: This should instead be accomplished programmatically by\r
+  //        ennumerating all PCI devices present in the system and\r
+  //        computing PCI_INTERRUPT_LINE from PCI_INTERRUPT_PIN, the\r
+  //        slot/position of the device, and the available host IRQs\r
+  //        (for an example, see SeaBIOS pci_bios_init_devices() in\r
+  //        src/fw/pciinit.c)\r
   //\r
-  IoOr16 ((PciRead32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40)) & ~BIT0) + 4, BIT0);\r
+  switch (HostBridgeDevId) {\r
+    case INTEL_82441_DEVICE_ID:\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    1, 2, 0x3c), 0x0b); // usb (northbr.)\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    1, 3, 0x3c), 0x0a); // acpi (northbr.)\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    3, 0, 0x3c), 0x0b);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    4, 0, 0x3c), 0x0b);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    5, 0, 0x3c), 0x0a);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    6, 0, 0x3c), 0x0a);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    7, 0, 0x3c), 0x0b);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    8, 0, 0x3c), 0x0b);\r
+      break;\r
+    case INTEL_Q35_MCH_DEVICE_ID:\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    2, 0, 0x3c), 0x0b);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    3, 0, 0x3c), 0x0b);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    4, 0, 0x3c), 0x0a);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    5, 0, 0x3c), 0x0a);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    6, 0, 0x3c), 0x0b);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    7, 0, 0x3c), 0x0b);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0,    8, 0, 0x3c), 0x0a);\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 0, 0x3c), 0x0a); // uhci1\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 1, 0x3c), 0x0a); // uhci2\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 2, 0x3c), 0x0b); // uhci3\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1d, 7, 0x3c), 0x0b); // ehci1\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 2, 0x3c), 0x0a); // ahci (northbr.)\r
+      PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 3, 0x3c), 0x0a); // smbus (northbr.)\r
+      break;\r
+    default:\r
+      ASSERT (FALSE); // should never be reached\r
+  }\r
 }\r
 \r
 \r
@@ -938,8 +967,7 @@ Returns:
   //\r
   BdsLibConnectAll ();\r
 \r
-  PciInitialization ();\r
-  AcpiInitialization ();\r
+  PciAcpiInitialization ();\r
 \r
   //\r
   // Clear the logo after all devices are connected.\r

diff --git a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.h b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.h
index 72b0e149e0534db3f6df6a9d20be11ced0306e1a..7006fb379521c086ea57e451efa4b0faf63d7fcf 100644 (file)
--- a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.h
+++ b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.h
@@ -59,6 +59,8 @@ Abstract:
 #include <Guid/HobList.h>\r
 #include <Guid/GlobalVariable.h>\r
 \r
+#include <OvmfPlatforms.h>\r
+\r
 extern BDS_CONSOLE_CONNECT_ENTRY  gPlatformConsole[];\r
 extern EFI_DEVICE_PATH_PROTOCOL   *gPlatformConnectSequence[];\r
 extern EFI_DEVICE_PATH_PROTOCOL   *gPlatformDriverOption[];\r

diff --git a/OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf b/OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
index a2b72bad3589990357423c9b68de7fb3254d1807..03f5b229cfc2b7ad0452e3c95253147dbaedc080 100644 (file)
--- a/OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
+++ b/OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
@@ -58,6 +58,7 @@
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile\r
   gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId\r
 \r
 [Pcd.IA32, Pcd.X64]\r
   gEfiMdePkgTokenSpaceGuid.PcdFSBClock\r