\r
\r
#define SIGN(_U) ((_U) ? "" : "-")\r
-#define WRITE(_W) ((_W) ? "!" : "")\r
+#define WRITE(_Write) ((_Write) ? "!" : "")\r
#define BYTE(_B) ((_B) ? "B":"")\r
#define USER(_B) ((_B) ? "^" : "")\r
\r
)\r
{\r
UINT32 OpCode;\r
- CHAR8 *Type, *Root;\r
- BOOLEAN I, P, U, B, W, L, S, H;\r
+ CHAR8 *Type;\r
+ CHAR8 *Root;\r
+ BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;\r
UINT32 Rn, Rd, Rm;\r
- UINT32 imode, offset_8, offset_12;\r
+ UINT32 IMod, Offset8, Offset12;\r
UINT32 Index;\r
- UINT32 shift_imm, shift;\r
+ UINT32 ShiftImm, Shift;\r
\r
OpCode = **OpCodePtr;\r
\r
- I = (OpCode & BIT25) == BIT25;\r
- P = (OpCode & BIT24) == BIT24;\r
- U = (OpCode & BIT23) == BIT23;\r
- B = (OpCode & BIT22) == BIT22; // Also called S\r
- W = (OpCode & BIT21) == BIT21;\r
- L = (OpCode & BIT20) == BIT20;\r
- S = (OpCode & BIT6) == BIT6;\r
- H = (OpCode & BIT5) == BIT5;\r
+ Imm = (OpCode & BIT25) == BIT25; // I\r
+ Pre = (OpCode & BIT24) == BIT24; // P\r
+ Up = (OpCode & BIT23) == BIT23; // U\r
+ WriteBack = (OpCode & BIT22) == BIT22; // B, also called S\r
+ Write = (OpCode & BIT21) == BIT21; // W\r
+ Load = (OpCode & BIT20) == BIT20; // L\r
+ Sign = (OpCode & BIT6) == BIT6; // S\r
+ Half = (OpCode & BIT5) == BIT5; // H\r
Rn = (OpCode >> 16) & 0xf;\r
Rd = (OpCode >> 12) & 0xf;\r
Rm = (OpCode & 0xf);\r
\r
// LDREX, STREX\r
if ((OpCode & 0x0fe000f0) == 0x01800090) {\r
- if (L) {\r
+ if (Load) {\r
// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]\r
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);\r
} else {\r
\r
// LDM/STM\r
if ((OpCode & 0x0e000000) == 0x08000000) {\r
- if (L) {\r
+ if (Load) {\r
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^\r
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^\r
- AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));\r
+ AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));\r
} else {\r
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^\r
- AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));\r
+ AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));\r
}\r
return;\r
}\r
\r
// LDR/STR Address Mode 2\r
if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {\r
- offset_12 = OpCode & 0xfff;\r
+ Offset12 = OpCode & 0xfff;\r
if ((OpCode & 0xfd70f000 ) == 0xf550f000) {\r
Index = AsciiSPrint (Buf, Size, "PLD");\r
} else {\r
- Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);\r
+ Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);\r
}\r
- if (P) {\r
- if (!I) {\r
+ if (Pre) {\r
+ if (!Imm) {\r
// A5.2.2 [<Rn>, #+/-<offset_12>]\r
// A5.2.5 [<Rn>, #+/-<offset_12>]\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (U), offset_12, WRITE (W));\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (Up), Offset12, WRITE (Write));\r
} else if ((OpCode & 0x03000ff0) == 0x03000000) {\r
// A5.2.3 [<Rn>, +/-<Rm>]\r
// A5.2.6 [<Rn>, +/-<Rm>]!\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (U), WRITE (W));\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (Up), WRITE (Write));\r
} else {\r
// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]\r
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!\r
- shift_imm = (OpCode >> 7) & 0x1f;\r
- shift = (OpCode >> 5) & 0x3;\r
- if (shift == 0x0) {\r
+ ShiftImm = (OpCode >> 7) & 0x1f;\r
+ Shift = (OpCode >> 5) & 0x3;\r
+ if (Shift == 0x0) {\r
Type = "LSL";\r
- } else if (shift == 0x1) {\r
+ } else if (Shift == 0x1) {\r
Type = "LSR";\r
- if (shift_imm == 0) {\r
- shift_imm = 32;\r
+ if (ShiftImm == 0) {\r
+ ShiftImm = 32;\r
}\r
- } else if (shift == 0x2) {\r
+ } else if (Shift == 0x2) {\r
Type = "ASR";\r
- } else if (shift_imm == 0) {\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));\r
+ } else if (ShiftImm == 0) {\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));\r
return;\r
} else {\r
Type = "ROR";\r
}\r
\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));\r
}\r
- } else { // !P\r
- if (!I) {\r
+ } else { // !Pre\r
+ if (!Imm) {\r
// A5.2.8 [<Rn>], #+/-<offset_12>\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (U), offset_12);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);\r
} else if ((OpCode & 0x03000ff0) == 0x03000000) {\r
// A5.2.9 [<Rn>], +/-<Rm>\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);\r
} else {\r
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>\r
- shift_imm = (OpCode >> 7) & 0x1f;\r
- shift = (OpCode >> 5) & 0x3;\r
+ ShiftImm = (OpCode >> 7) & 0x1f;\r
+ Shift = (OpCode >> 5) & 0x3;\r
\r
- if (shift == 0x0) {\r
+ if (Shift == 0x0) {\r
Type = "LSL";\r
- } else if (shift == 0x1) {\r
+ } else if (Shift == 0x1) {\r
Type = "LSR";\r
- if (shift_imm == 0) {\r
- shift_imm = 32;\r
+ if (ShiftImm == 0) {\r
+ ShiftImm = 32;\r
}\r
- } else if (shift == 0x2) {\r
+ } else if (Shift == 0x2) {\r
Type = "ASR";\r
- } else if (shift_imm == 0) {\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]);\r
+ } else if (ShiftImm == 0) {\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (Up), gReg[Rm]);\r
// FIx me\r
return;\r
} else {\r
Type = "ROR";\r
}\r
\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);\r
}\r
}\r
return;\r
if ((OpCode & 0x0e000000) == 0x00000000) {\r
// LDR/STR address mode 3\r
// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>\r
- if (L) {\r
- if (!S) {\r
+ if (Load) {\r
+ if (!Sign) {\r
Root = "LDR%aH %a, ";\r
- } else if (!H) {\r
+ } else if (!Half) {\r
Root = "LDR%aSB %a, ";\r
} else {\r
Root = "LDR%aSH %a, ";\r
}\r
} else {\r
- if (!S) {\r
+ if (!Sign) {\r
Root = "STR%aH %a ";\r
- } else if (!H) {\r
+ } else if (!Half) {\r
Root = "LDR%aD %a ";\r
} else {\r
Root = "STR%aD %a ";\r
\r
Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);\r
\r
- S = (OpCode & BIT6) == BIT6;\r
- H = (OpCode & BIT5) == BIT5;\r
- offset_8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;\r
- if (P & !W) {\r
+ Sign = (OpCode & BIT6) == BIT6;\r
+ Half = (OpCode & BIT5) == BIT5;\r
+ Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;\r
+ if (Pre & !Write) {\r
// Immediate offset/index\r
- if (B) {\r
+ if (WriteBack) {\r
// A5.3.2 [<Rn>, #+/-<offset_8>]\r
// A5.3.4 [<Rn>, #+/-<offset_8>]!\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (U), offset_8, WRITE (W));\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));\r
} else {\r
// A5.3.3 [<Rn>, +/-<Rm>]\r
// A5.3.5 [<Rn>, +/-<Rm>]!\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));\r
}\r
} else {\r
// Register offset/index\r
- if (B) {\r
+ if (WriteBack) {\r
// A5.3.6 [<Rn>], #+/-<offset_8>\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (U), offset_8);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);\r
} else {\r
// A5.3.7 [<Rn>], +/-<Rm>\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);\r
}\r
}\r
return;\r
if ((OpCode & 0x0fb000f0) == 0x01000050) {\r
// A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]\r
// A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>]\r
- AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);\r
+ AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (WriteBack), gReg[Rd], gReg[Rm], gReg[Rn]);\r
return;\r
}\r
\r
if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {\r
// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}\r
- AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));\r
+ AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (Write));\r
return;\r
}\r
\r
if ((OpCode & 0xfe500f00) == 0xf8100500) {\r
// A4.1.59 RFE<addressing_mode> <Rn>{!}\r
- AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));\r
+ AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (Write));\r
return;\r
}\r
\r
if (((OpCode >> 6) & 0x7) == 0) {\r
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));\r
} else {\r
- imode = (OpCode >> 18) & 0x3;\r
+ IMod = (OpCode >> 18) & 0x3;\r
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",\r
- (imode == 3) ? "ID":"IE",\r
+ (IMod == 3) ? "ID":"IE",\r
((OpCode & BIT8) != 0) ? "A":"",\r
((OpCode & BIT7) != 0) ? "I":"",\r
((OpCode & BIT6) != 0) ? "F":"");\r
\r
if ((OpCode & 0x0fb00000) == 0x01000000) {\r
// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR\r
- AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");\r
+ AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], WriteBack ? "SPSR" : "CPSR");\r
return;\r
}\r
\r
\r
if ((OpCode & 0x0db00000) == 0x01200000) {\r
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>\r
- if (I) {\r
+ if (Imm) {\r
// MSR{<cond>} CPSR_<fields>, #<immediate>\r
- AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), B ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));\r
+ AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));\r
} else {\r
// MSR{<cond>} CPSR_<fields>, <Rm>\r
- AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);\r
+ AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);\r
}\r
return;\r
}\r
if ((OpCode & 0x0e000000) == 0x0c000000) {\r
// A4.1.19 LDC and A4.1.96 SDC\r
if ((OpCode & 0xf0000000) == 0xf0000000) {\r
- Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);\r
+ Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);\r
} else {\r
- Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);\r
+ Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);\r
}\r
\r
- if (!P) {\r
- if (!W) {\r
+ if (!Pre) {\r
+ if (!Write) {\r
// A5.5.5.5 [<Rn>], <option>\r
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);\r
} else {\r
// A.5.5.4 [<Rn>], #+/-<offset_8>*4\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);\r
}\r
} else {\r
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));\r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));\r
}\r
\r
}\r
\r
if ((OpCode & 0x0f000010) == 0x0e000010) {\r
// A4.1.32 MRC2, MCR2\r
- AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);\r
+ AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);\r
return;\r
}\r
\r
if ((OpCode & 0x0ff00000) == 0x0c400000) {\r
// A4.1.33 MRRC2, MCRR2\r
- AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);\r
+ AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);\r
return;\r
}\r
\r
try to reuse existing case entries if possible.\r
\r
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
// in the instruction address and you get back the aligned answer\r
//\r
UINT32\r
-PCAlign4 (\r
+PcAlign4 (\r
IN UINT32 Data\r
)\r
{\r
UINT32 Index;\r
UINT32 Offset;\r
UINT16 Rd, Rn, Rm, Rt, Rt2;\r
- BOOLEAN H1, H2, imod;\r
+ BOOLEAN H1Bit; // H1\r
+ BOOLEAN H2Bit; // H2\r
+ BOOLEAN IMod; // imod\r
//BOOLEAN ItFlag;\r
- UINT32 PC, Target, msbit, lsbit;\r
+ UINT32 Pc, Target, MsBit, LsBit;\r
CHAR8 *Cond;\r
- BOOLEAN S, J1, J2, P, U, W;\r
- UINT32 coproc, opc1, opc2, CRd, CRn, CRm;\r
+ BOOLEAN Sign; // S\r
+ BOOLEAN J1Bit; // J1\r
+ BOOLEAN J2Bit; // J2\r
+ BOOLEAN Pre; // P\r
+ BOOLEAN UAdd; // U\r
+ BOOLEAN WriteBack; // W\r
+ UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;\r
UINT32 Mask;\r
\r
OpCodePtr = *OpCodePtrPtr;\r
Rd = OpCode & 0x7;\r
Rn = (OpCode >> 3) & 0x7;\r
Rm = (OpCode >> 6) & 0x7;\r
- H1 = (OpCode & BIT7) != 0;\r
- H2 = (OpCode & BIT6) != 0;\r
- imod = (OpCode & BIT4) != 0;\r
- PC = (UINT32)(UINTN)OpCodePtr;\r
+ H1Bit = (OpCode & BIT7) != 0;\r
+ H2Bit = (OpCode & BIT6) != 0;\r
+ IMod = (OpCode & BIT4) != 0;\r
+ Pc = (UINT32)(UINTN)OpCodePtr;\r
\r
// Increment by the minimum instruction size, Thumb2 could be bigger\r
*OpCodePtrPtr += 1;\r
case LOAD_STORE_FORMAT3:\r
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);\r
return;\r
case LOAD_STORE_FORMAT4:\r
// Rt, [SP, #imm8]\r
Cond = gCondition[(OpCode >> 8) & 0xf];\r
Buf[Offset-5] = *Cond++;\r
Buf[Offset-4] = *Cond;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));\r
return;\r
case UNCONDITIONAL_BRANCH_SHORT:\r
// A6.3.2 B <target_address>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));\r
return;\r
\r
case BRANCH_EXCHANGE:\r
// A6.3.3 BX|BLX <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);\r
return;\r
\r
case DATA_FORMAT1:\r
return;\r
case DATA_FORMAT8:\r
// A6.4.3 <Rd>|<Rn>, <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);\r
return;\r
\r
case CPS_FORMAT:\r
// A7.1.24\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");\r
return;\r
\r
case ENDIAN_FORMAT:\r
case DATA_CBZ:\r
// CB{N}Z <Rn>, <Lable>\r
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);\r
return;\r
\r
case ADR_FORMAT:\r
// ADR <Rd>, <Label>\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);\r
return;\r
\r
case IT_BLOCK:\r
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1\r
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S\r
Target = SignExtend32 (Target, BIT20);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);\r
return;\r
case B_T4:\r
// S:I1:I2:imm10:imm11:0\r
Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);\r
- S = (OpCode32 & BIT26) == BIT26;\r
- J1 = (OpCode32 & BIT13) == BIT13;\r
- J2 = (OpCode32 & BIT11) == BIT11;\r
- Target |= (!(J2 ^ S) ? BIT22 : 0); // I2\r
- Target |= (!(J1 ^ S) ? BIT23 : 0); // I1\r
- Target |= (S ? BIT24 : 0); // S\r
+ Sign = (OpCode32 & BIT26) == BIT26;\r
+ J1Bit = (OpCode32 & BIT13) == BIT13;\r
+ J2Bit = (OpCode32 & BIT11) == BIT11;\r
+ Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2\r
+ Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1\r
+ Target |= (Sign ? BIT24 : 0); // S\r
Target = SignExtend32 (Target, BIT24);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);\r
return;\r
\r
case BL_T2:\r
// BLX S:I1:I2:imm10:imm11:0\r
Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);\r
- S = (OpCode32 & BIT26) == BIT26;\r
- J1 = (OpCode32 & BIT13) == BIT13;\r
- J2 = (OpCode32 & BIT11) == BIT11;\r
- Target |= (!(J2 ^ S) ? BIT23 : 0); // I2\r
- Target |= (!(J1 ^ S) ? BIT24 : 0); // I1\r
- Target |= (S ? BIT25 : 0); // S\r
+ Sign = (OpCode32 & BIT26) == BIT26;\r
+ J1Bit = (OpCode32 & BIT13) == BIT13;\r
+ J2Bit = (OpCode32 & BIT11) == BIT11;\r
+ Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2\r
+ Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1\r
+ Target |= (Sign ? BIT25 : 0); // S\r
Target = SignExtend32 (Target, BIT25);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);\r
return;\r
\r
case POP_T2:\r
\r
case STM_FORMAT:\r
// <Rn>{!}, <registers>\r
- W = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));\r
return;\r
\r
case LDM_REG_IMM12_SIGNED:\r
// U == 0 means subtrack, U == 1 means add\r
Target = -Target;\r
}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);\r
return;\r
\r
case LDM_REG_INDIRECT_LSL:\r
\r
case LDM_REG_IMM8:\r
// <rt>, [<rn>, {, #<imm8>}]{!}\r
- W = (OpCode32 & BIT8) == BIT8;\r
- U = (OpCode32 & BIT9) == BIT9;\r
- P = (OpCode32 & BIT10) == BIT10;\r
+ WriteBack = (OpCode32 & BIT8) == BIT8;\r
+ UAdd = (OpCode32 & BIT9) == BIT9;\r
+ Pre = (OpCode32 & BIT10) == BIT10;\r
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
- if (P) {\r
+ if (Pre) {\r
if ((OpCode32 & 0xff) == 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-" , OpCode32 & 0xff, W?"!":"");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");\r
}\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", U?"":"-", OpCode32 & 0xff);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);\r
}\r
return;\r
\r
case LDRD_REG_IMM8_SIGNED:\r
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
- P = (OpCode32 & BIT24) == BIT24; // index = P\r
- U = (OpCode32 & BIT23) == BIT23;\r
- W = (OpCode32 & BIT21) == BIT21;\r
+ Pre = (OpCode32 & BIT24) == BIT24; // index = P\r
+ UAdd = (OpCode32 & BIT23) == BIT23;\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
- if (P) {\r
+ if (Pre) {\r
if ((OpCode32 & 0xff) == 0) {\r
AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-", (OpCode32 & 0xff) << 2, W?"!":"");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");\r
}\r
} else {\r
if ((OpCode32 & 0xff) != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", U?"":"-", (OpCode32 & 0xff) << 2);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);\r
}\r
}\r
return;\r
// U == 0 means subtrack, U == 1 means add\r
Target = -Target;\r
}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], PC + 4 + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);\r
return;\r
\r
case LDREXB:\r
\r
case SRS_FORMAT:\r
// SP{!}, #<mode>\r
- W = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", W?"!":"", OpCode32 & 0x1f);\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);\r
return;\r
\r
case RFE_FORMAT:\r
// <Rn>{!}\r
- W = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");\r
return;\r
\r
case ADD_IMM12:\r
// ADDR <Rd>, <label>\r
Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {\r
- Target = PCAlign4 (PC) - Target;\r
+ Target = PcAlign4 (Pc) - Target;\r
} else {\r
- Target = PCAlign4 (PC) + Target;\r
+ Target = PcAlign4 (Pc) + Target;\r
}\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);\r
return;\r
\r
case BFC_THUMB2:\r
// BFI <Rd>, <Rn>, #<lsb>, #<width>\r
- msbit = OpCode32 & 0x1f;\r
- lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);\r
+ MsBit = OpCode32 & 0x1f;\r
+ LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);\r
if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){\r
// BFC <Rd>, #<lsb>, #<width>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);\r
} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);\r
}\r
return;\r
\r
case CPD_THUMB2:\r
// <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
- coproc = (OpCode32 >> 8) & 0xf;\r
- opc1 = (OpCode32 >> 20) & 0xf;\r
- opc2 = (OpCode32 >> 5) & 0x7;\r
+ Coproc = (OpCode32 >> 8) & 0xf;\r
+ Opc1 = (OpCode32 >> 20) & 0xf;\r
+ Opc2 = (OpCode32 >> 5) & 0x7;\r
CRd = (OpCode32 >> 12) & 0xf;\r
CRn = (OpCode32 >> 16) & 0xf;\r
CRm = OpCode32 & 0xf;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", coproc, opc1, CRd, CRn, CRm);\r
- if (opc2 != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);\r
+ if (Opc2 != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);\r
}\r
return;\r
\r
case MRC_THUMB2:\r
// MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
- coproc = (OpCode32 >> 8) & 0xf;\r
- opc1 = (OpCode32 >> 20) & 0xf;\r
- opc2 = (OpCode32 >> 5) & 0x7;\r
+ Coproc = (OpCode32 >> 8) & 0xf;\r
+ Opc1 = (OpCode32 >> 20) & 0xf;\r
+ Opc2 = (OpCode32 >> 5) & 0x7;\r
CRn = (OpCode32 >> 16) & 0xf;\r
CRm = OpCode32 & 0xf;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm);\r
- if (opc2 != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);\r
+ if (Opc2 != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);\r
}\r
return;\r
\r
case MRRC_THUMB2:\r
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>\r
- coproc = (OpCode32 >> 8) & 0xf;\r
- opc1 = (OpCode32 >> 20) & 0xf;\r
+ Coproc = (OpCode32 >> 8) & 0xf;\r
+ Opc1 = (OpCode32 >> 20) & 0xf;\r
CRn = (OpCode32 >> 16) & 0xf;\r
CRm = OpCode32 & 0xf;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);\r
return;\r
\r
case THUMB2_2REGS:\r
projects / mirror_edk2.git / commitdiff