//\r
UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);\r
\r
- Shift = (UINTN) ((Address - AccessAddress) * 8);\r
+ Shift = (UINTN)(Address - AccessAddress) * 8;\r
switch (Width) {\r
case EfiPciWidthUint8:\r
Data = (* (UINT8 *) Buffer) << Shift | (Data & ~(0xff << Shift));\r
//\r
// check data write incompatibility\r
//\r
- UpdateConfigData (PciDeviceInfo, PCI_REGISTER_WRITE, AccessWidth, AccessAddress * 0xff, &Data);\r
+ UpdateConfigData (PciDeviceInfo, PCI_REGISTER_WRITE, AccessWidth, MultU64x32 (AccessAddress, 0xff), &Data);\r
}\r
\r
if (PciRootBridgeIo != NULL) {\r