#/** @file\r
-# Instance of Cache Maintenance Library using Base Library services.\r
+# Instance of Cache Maintenance Library using Base Library services.\r
#\r
-# Cache Maintenance Library that uses Base Library services to maintain caches.\r
+# Cache Maintenance Library that uses Base Library services to maintain caches.\r
# This library assumes there are no chipset dependencies required to maintain caches.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation\r
+# Copyright (c) 2007 - 2008, Intel Corporation\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of CPU Library for various architecture.\r
+# Instance of CPU Library for various architecture.\r
#\r
-# CPU Library implemented using ASM functions for IA-32 and X64,\r
-# PAL CALLs for IPF, and empty functions for EBC.\r
+# CPU Library implemented using ASM functions for IA-32 and X64,\r
+# PAL CALLs for IPF, and empty functions for EBC.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Debug Library with empty functions.\r
+# Debug Library with empty functions.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of I/O Library using compiler intrinsics.\r
+# Instance of I/O Library using compiler intrinsics.\r
#\r
-# I/O Library that uses compiler intrinsics to perform IN and OUT instructions\r
-# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.\r
-# MMIO requests are forwarded directly to memory.\r
+# I/O Library that uses compiler intrinsics to perform IN and OUT instructions\r
+# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.\r
+# MMIO requests are forwarded directly to memory.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Base Library implementation.\r
+# Base Library implementation.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of Base Memory Library without assembly.\r
+# Instance of Base Memory Library without assembly.\r
#\r
-# Base Memory Library implementation - no ASM.\r
+# Base Memory Library implementation - no ASM.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of Base Memory Library using MMX registers.\r
+# Instance of Base Memory Library using MMX registers.\r
#\r
-# Base Memory Library that uses MMX registers for high performance.\r
+# Base Memory Library that uses MMX registers for high performance.\r
# Optimized for use in DXE.\r
#\r
-# Copyright (c) 2006 - 2008, Intel Corporation\r
+# Copyright (c) 2006 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of Base Memory Library optimized for use in DXE phase.\r
+# Instance of Base Memory Library optimized for use in DXE phase.\r
#\r
-# Base Memory Library that is optimized for use in DXE phase. \r
-# Uses REP, MMX, XMM registers as required for best performance.\r
+# Base Memory Library that is optimized for use in DXE phase. \r
+# Uses REP, MMX, XMM registers as required for best performance.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of Base Memory Library optimized for use in PEI phase.\r
+# Instance of Base Memory Library optimized for use in PEI phase.\r
#\r
-# Base Memory Library that is optimized for use in PEI phase. \r
-# Uses REP, MMX, XMM registers as required for best performance.\r
+# Base Memory Library that is optimized for use in PEI phase. \r
+# Uses REP, MMX, XMM registers as required for best performance.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of Base Memory Library using REP string instructions.\r
+# Instance of Base Memory Library using REP string instructions.\r
#\r
-# Base Memory Library that uses REP string instructions for\r
+# Base Memory Library that uses REP string instructions for\r
# high performance and small size. Optimized for use in PEI.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of Base Memory Library using XMM registers.\r
+# Instance of Base Memory Library using XMM registers.\r
#\r
-# Base Memory Library that uses XMM registers for high performance.\r
+# Base Memory Library that uses XMM registers for high performance.\r
# Optimized for use in DXE.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Null instance of PAL Library with empty functions.\r
+# Null instance of PAL Library with empty functions.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of PCD Library without support of dynamic PCD entries.\r
+# Instance of PCD Library without support of dynamic PCD entries.\r
#\r
-# PCD Library that only provides access to Feature Flag, Fixed At Build,\r
-# and Binary Patch typed PCD entries. Access to Dynamic PCD entries is ignored.\r
+# PCD Library that only provides access to Feature Flag, Fixed At Build,\r
+# and Binary Patch typed PCD entries. Access to Dynamic PCD entries is ignored.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of PCI CF8 Library using I/O ports 0xCF8 and 0xCFC.\r
+# Instance of PCI CF8 Library using I/O ports 0xCF8 and 0xCFC.\r
#\r
-# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.\r
+# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.\r
# Layers on top of an I/O Library instance.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.\r
+# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.\r
#\r
-# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform\r
+# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform\r
# PCI Configuration cycles. Layers on top of an I/O Library instance.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of PCI Library based on PCI CF8 Library.\r
+# Instance of PCI Library based on PCI CF8 Library.\r
#\r
-# PCI Library that uses I/O ports 0xCF8 and 0xCFC to perform\r
+# PCI Library that uses I/O ports 0xCF8 and 0xCFC to perform\r
# PCI Configuration cycles. Layers on top of one PCI CF8 Library instance.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of PCI Library based on PCI Express Library.\r
+# Instance of PCI Library based on PCI Express Library.\r
#\r
-# PCI Library that uses the 256 MB PCI Express MMIO window to perform PCI\r
+# PCI Library that uses the 256 MB PCI Express MMIO window to perform PCI\r
# Configuration cycles. Layers on one PCI Express Library instance.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# PE/COFF Entry Point Library implementation.\r
+# PE/COFF Entry Point Library implementation.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# PE/COFF Loader Library implementation.\r
+# PE/COFF Loader Library implementation.\r
#\r
-# Copyright (c) 2006 - 2008, Intel Corporation.\r
+# Copyright (c) 2006 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of Performance Library based on Base Library.\r
+# Instance of Performance Library based on Base Library.\r
#\r
-# Performance Library that layers on top of the Base Library to measure start\r
+# Performance Library that layers on top of the Base Library to measure start\r
# and end times using CPU specific timer services if they are available.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of Post Code Library based on Debug Library.\r
+# Instance of Post Code Library based on Debug Library.\r
#\r
-# Post Code Library that layers on top of a Debug Library instance.\r
+# Post Code Library that layers on top of a Debug Library instance.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Instance of Post Code Library using I/O port 0x80.\r
+# Instance of Post Code Library using I/O port 0x80.\r
#\r
-# Post Code Library that writes post code values to I/O port 0x80.\r
+# Post Code Library that writes post code values to I/O port 0x80.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# Print Library implementation.\r
+# Print Library implementation.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#/** @file\r
-# NULL instance of Timer Library as a template.\r
+# NULL instance of Timer Library as a template.\r
#\r
-# A non-functional instance of the Timer Library that can be used as a template\r
+# A non-functional instance of the Timer Library that can be used as a template\r
# for the implementation of a functional timer library instance. This library instance can\r
# also be used to test build DXE, Runtime, DXE SAL, and DXE SMM modules that require timer\r
# services as well as EBC modules that require timer services.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
}\r
\r
for (Index = 0; Index < NumOfChar; Index++) {\r
+ ASSERT (BitLen[Index] != 0);\r
Count[BitLen[Index]]++;\r
}\r
\r
#/** @file\r
-# UEFI Decompress Library implementation.\r
+# UEFI Decompress Library implementation.\r
#\r
-# Copyright (c) 2007 - 2008, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r