RVCT is obsolete and no longer used.
Remove support for it.
Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
\r
[Sources.ARM]\r
GicV3/Arm/ArmGicV3.S | GCC\r
- GicV3/Arm/ArmGicV3.asm | RVCT\r
\r
[Sources.AARCH64]\r
GicV3/AArch64/ArmGicV3.S\r
+++ /dev/null
-//\r
-// Copyright (c) 2014, ARM Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//\r
-\r
-// For the moment we assume this will run in SVC mode on ARMv7\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
-//UINT32\r
-//EFIAPI\r
-//ArmGicGetControlSystemRegisterEnable (\r
-// VOID\r
-// );\r
- RVCT_ASM_EXPORT ArmGicV3GetControlSystemRegisterEnable\r
- mrc p15, 0, r0, c12, c12, 5 // ICC_SRE\r
- bx lr\r
-\r
-//VOID\r
-//EFIAPI\r
-//ArmGicSetControlSystemRegisterEnable (\r
-// IN UINT32 ControlSystemRegisterEnable\r
-// );\r
- RVCT_ASM_EXPORT ArmGicV3SetControlSystemRegisterEnable\r
- mcr p15, 0, r0, c12, c12, 5 // ICC_SRE\r
- isb\r
- bx lr\r
-\r
-//VOID\r
-//ArmGicV3EnableInterruptInterface (\r
-// VOID\r
-// );\r
- RVCT_ASM_EXPORT ArmGicV3EnableInterruptInterface\r
- mov r0, #1\r
- mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
- bx lr\r
-\r
-//VOID\r
-//ArmGicV3DisableInterruptInterface (\r
-// VOID\r
-// );\r
- RVCT_ASM_EXPORT ArmGicV3DisableInterruptInterface\r
- mov r0, #0\r
- mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
- bx lr\r
-\r
-//VOID\r
-//ArmGicV3EndOfInterrupt (\r
-// IN UINTN InterruptId\r
-// );\r
- RVCT_ASM_EXPORT ArmGicV3EndOfInterrupt\r
- mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1\r
- bx lr\r
-\r
-//UINTN\r
-//ArmGicV3AcknowledgeInterrupt (\r
-// VOID\r
-// );\r
- RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt\r
- mrc p15, 0, r0, c12, c12, 0 //ICC_IAR1\r
- bx lr\r
-\r
-//VOID\r
-//ArmGicV3SetPriorityMask (\r
-// IN UINTN Priority\r
-// );\r
- RVCT_ASM_EXPORT ArmGicV3SetPriorityMask\r
- mcr p15, 0, r0, c4, c6, 0 //ICC_PMR\r
- bx lr\r
-\r
-//VOID\r
-//ArmGicV3SetBinaryPointer (\r
-// IN UINTN BinaryPoint\r
-// );\r
- RVCT_ASM_EXPORT ArmGicV3SetBinaryPointer\r
- mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-;%HEADER%\r
-;/** @file\r
-; Macros to centralize the EXPORT, AREA, and definition of an assembly\r
-; function. The AREA prefix is required to put the function in its own\r
-; section so that removal of unused functions in the final link is performed.\r
-; This provides equivalent functionality to the compiler's --split-sections\r
-; option.\r
-;\r
-; Copyright (c) 2015 HP Development Company, L.P.\r
-;\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-;**/\r
-\r
-\r
- MACRO\r
- RVCT_ASM_EXPORT $func\r
- EXPORT $func\r
- AREA s_$func, CODE, READONLY\r
-$func\r
- MEND\r
-\r
- END\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Use ARMv6 instruction to operate on a single stack\r
-//\r
-// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2014, ARM Limited. All rights reserved.<BR>\r
-// Copyright (c) 2016 HP Development Company, L.P.<BR>\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-#include <Library/PcdLib.h>\r
-\r
-/*\r
-\r
-This is the stack constructed by the exception handler (low address to high address)\r
- # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM\r
- Reg Offset\r
- === ======\r
- R0 0x00 # stmfd SP!,{R0-R12}\r
- R1 0x04\r
- R2 0x08\r
- R3 0x0c\r
- R4 0x10\r
- R5 0x14\r
- R6 0x18\r
- R7 0x1c\r
- R8 0x20\r
- R9 0x24\r
- R10 0x28\r
- R11 0x2c\r
- R12 0x30\r
- SP 0x34 # reserved via subtraction 0x20 (32) from SP\r
- LR 0x38\r
- PC 0x3c\r
- CPSR 0x40\r
- DFSR 0x44\r
- DFAR 0x48\r
- IFSR 0x4c\r
- IFAR 0x50\r
-\r
- LR 0x54 # SVC Link register (we need to restore it)\r
-\r
- LR 0x58 # pushed by srsfd\r
- CPSR 0x5c\r
-\r
- */\r
-\r
-\r
- EXPORT ExceptionHandlersStart\r
- EXPORT ExceptionHandlersEnd\r
- EXPORT CommonExceptionEntry\r
- EXPORT AsmCommonExceptionEntry\r
- IMPORT CommonCExceptionHandler\r
-\r
- PRESERVE8\r
- AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5\r
-\r
-//\r
-// This code gets copied to the ARM vector table\r
-// ExceptionHandlersStart - ExceptionHandlersEnd gets copied\r
-//\r
-ExceptionHandlersStart\r
-\r
-Reset\r
- b ResetEntry\r
-\r
-UndefinedInstruction\r
- b UndefinedInstructionEntry\r
-\r
-SoftwareInterrupt\r
- b SoftwareInterruptEntry\r
-\r
-PrefetchAbort\r
- b PrefetchAbortEntry\r
-\r
-DataAbort\r
- b DataAbortEntry\r
-\r
-ReservedException\r
- b ReservedExceptionEntry\r
-\r
-Irq\r
- b IrqEntry\r
-\r
-Fiq\r
- b FiqEntry\r
-\r
-ResetEntry\r
- srsfd #0x13! ; Store return state on SVC stack\r
- ; We are already in SVC mode\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#0 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-UndefinedInstructionEntry\r
- sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#1 ; ExceptionType\r
- ldr R1,CommonExceptionEntry;\r
- bx R1\r
-\r
-SoftwareInterruptEntry\r
- srsfd #0x13! ; Store return state on SVC stack\r
- ; We are already in SVC mode\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#2 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-PrefetchAbortEntry\r
- sub LR,LR,#4\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#3 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-DataAbortEntry\r
- sub LR,LR,#8\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#4 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-ReservedExceptionEntry\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#5 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-IrqEntry\r
- sub LR,LR,#4\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
-\r
- mov R0,#6 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-FiqEntry\r
- sub LR,LR,#4\r
- srsfd #0x13! ; Store return state on SVC stack\r
- cps #0x13 ; Switch to SVC for common stack\r
- stmfd SP!,{LR} ; Store the link register for the current mode\r
- sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR\r
- stmfd SP!,{R0-R12} ; Store the register state\r
- ; Since we have already switch to SVC R8_fiq - R12_fiq\r
- ; never get used or saved\r
- mov R0,#7 ; ExceptionType\r
- ldr R1,CommonExceptionEntry\r
- bx R1\r
-\r
-//\r
-// This gets patched by the C code that patches in the vector table\r
-//\r
-CommonExceptionEntry\r
- dcd AsmCommonExceptionEntry\r
-\r
-ExceptionHandlersEnd\r
-\r
-//\r
-// This code runs from CpuDxe driver loaded address. It is patched into\r
-// CommonExceptionEntry.\r
-//\r
-AsmCommonExceptionEntry\r
- mrc p15, 0, R1, c6, c0, 2 ; Read IFAR\r
- str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR\r
-\r
- mrc p15, 0, R1, c5, c0, 1 ; Read IFSR\r
- str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r
-\r
- mrc p15, 0, R1, c6, c0, 0 ; Read DFAR\r
- str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r
-\r
- mrc p15, 0, R1, c5, c0, 0 ; Read DFSR\r
- str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r
-\r
- ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack\r
- str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r
-\r
- add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
- and R3, R1, #0x1f ; Check CPSR to see if User or System Mode\r
- cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))\r
- cmpne R3, #0x10 ;\r
- stmeqed R2, {lr}^ ; save unbanked lr\r
- ; else\r
- stmneed R2, {lr} ; save SVC lr\r
-\r
-\r
- ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd\r
- ; Check to see if we have to adjust for Thumb entry\r
- sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType == 2)) {\r
- cmp r4, #1 ; // UND & SVC have different LR adjust for Thumb\r
- bhi NoAdjustNeeded\r
-\r
- tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry\r
- addne R5, R5, #2 ; PC += 2;\r
- strne R5,[SP,#0x58] ; Update LR value pushed by srsfd\r
-\r
-NoAdjustNeeded\r
-\r
- str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r
-\r
- add R1, SP, #0x60 ; We pushed 0x60 bytes on the stack\r
- str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r
-\r
- ; R0 is ExceptionType\r
- mov R1,SP ; R1 is SystemContext\r
-\r
-#if (FixedPcdGet32(PcdVFPEnabled))\r
- vpush {d0-d15} ; save vstm registers in case they are used in optimizations\r
-#endif\r
-\r
- mov R4, SP ; Save current SP\r
- tst R4, #4\r
- subne SP, SP, #4 ; Adjust SP if not 8-byte aligned\r
-\r
-/*\r
-VOID\r
-EFIAPI\r
-CommonCExceptionHandler (\r
- IN EFI_EXCEPTION_TYPE ExceptionType, R0\r
- IN OUT EFI_SYSTEM_CONTEXT SystemContext R1\r
- )\r
-\r
-*/\r
- blx CommonCExceptionHandler ; Call exception handler\r
-\r
- mov SP, R4 ; Restore SP\r
-\r
-#if (FixedPcdGet32(PcdVFPEnabled))\r
- vpop {d0-d15}\r
-#endif\r
-\r
- ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR\r
- mcr p15, 0, R1, c5, c0, 1 ; Write IFSR\r
-\r
- ldr R1, [SP, #0x44] ; Restore EFI_SYSTEM_CONTEXT_ARM.DFSR\r
- mcr p15, 0, R1, c5, c0, 0 ; Write DFSR\r
-\r
- ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC\r
- str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored\r
-\r
- ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR\r
- str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored\r
-\r
- add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry\r
- add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
- and R1, R1, #0x1f ; Check to see if User or System Mode\r
- cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))\r
- cmpne R1, #0x10 ;\r
- ldmeqed R2, {lr}^ ; restore unbanked lr\r
- ; else\r
- ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}\r
-\r
- ldmfd SP!,{R0-R12} ; Restore general purpose registers\r
- ; Exception handler can not change SP\r
-\r
- add SP,SP,#0x20 ; Clear out the remaining stack space\r
- ldmfd SP!,{LR} ; restore the link register for this context\r
- rfefd SP! ; return from exception via srsfd stack slot\r
-\r
- END\r
-\r
-\r
\r
[Sources.Arm]\r
Arm/ArmException.c\r
- Arm/ExceptionSupport.asm | RVCT\r
Arm/ExceptionSupport.S | GCC\r
\r
[Sources.AARCH64]\r
\r
[Sources.Arm]\r
Arm/ArmException.c\r
- Arm/ExceptionSupport.asm | RVCT\r
Arm/ExceptionSupport.S | GCC\r
\r
[Sources.AARCH64]\r
+++ /dev/null
-//\r
-// Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
-// Copyright (c) 2014, Linaro Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
- RVCT_ASM_EXPORT ArmCallHvc\r
- push {r4-r8}\r
- // r0 will be popped just after the HVC call\r
- push {r0}\r
-\r
- // Load the HVC arguments values into the appropriate registers\r
- ldr r7, [r0, #28]\r
- ldr r6, [r0, #24]\r
- ldr r5, [r0, #20]\r
- ldr r4, [r0, #16]\r
- ldr r3, [r0, #12]\r
- ldr r2, [r0, #8]\r
- ldr r1, [r0, #4]\r
- ldr r0, [r0, #0]\r
-\r
- hvc #0\r
-\r
- // Pop the ARM_HVC_ARGS structure address from the stack into r8\r
- pop {r8}\r
-\r
- // Load the HVC returned values into the appropriate registers\r
- // A HVC call can return up to 4 values - we do not need to store back r4-r7.\r
- str r3, [r8, #12]\r
- str r2, [r8, #8]\r
- str r1, [r8, #4]\r
- str r0, [r8, #0]\r
-\r
- mov r0, r8\r
-\r
- // Restore the registers r4-r8\r
- pop {r4-r8}\r
-\r
- bx lr\r
-\r
- END\r
LIBRARY_CLASS = ArmHvcLib\r
\r
[Sources.ARM]\r
- Arm/ArmHvc.asm | RVCT\r
Arm/ArmHvc.S | GCC\r
\r
[Sources.AARCH64]\r
[Packages]\r
MdePkg/MdePkg.dec\r
ArmPkg/ArmPkg.dec\r
-\r
-[BuildOptions]\r
- RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
- RVCT_ASM_EXPORT ArmReadMidr\r
- mrc p15,0,R0,c0,c0,0\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmCacheInfo\r
- mrc p15,0,R0,c0,c0,1\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmGetInterruptState\r
- mrs R0,CPSR\r
- tst R0,#0x80 // Check if IRQ is enabled.\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmGetFiqState\r
- mrs R0,CPSR\r
- tst R0,#0x40 // Check if FIQ is enabled.\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmSetDomainAccessControl\r
- mcr p15,0,r0,c3,c0,0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT CPSRMaskInsert\r
- stmfd sp!, {r4-r12, lr} // save all the banked registers\r
- mov r3, sp // copy the stack pointer into a non-banked register\r
- mrs r2, cpsr // read the cpsr\r
- bic r2, r2, r0 // clear mask in the cpsr\r
- and r1, r1, r0 // clear bits outside the mask in the input\r
- orr r2, r2, r1 // set field\r
- msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r
- isb\r
- mov sp, r3 // restore stack pointer\r
- ldmfd sp!, {r4-r12, lr} // restore registers\r
- bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r
-\r
- RVCT_ASM_EXPORT CPSRRead\r
- mrs r0, cpsr\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCpacr\r
- mrc p15, 0, r0, c1, c0, 2\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCpacr\r
- mcr p15, 0, r0, c1, c0, 2\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteAuxCr\r
- mcr p15, 0, r0, c1, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadAuxCr\r
- mrc p15, 0, r0, c1, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmSetTTBR0\r
- mcr p15,0,r0,c2,c0,0\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmSetTTBCR\r
- mcr p15, 0, r0, c2, c0, 2\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r
- mrc p15,0,r0,c2,c0,0\r
- MOV32 r1, 0xFFFFC000\r
- and r0, r0, r1\r
- isb\r
- bx lr\r
-\r
-//\r
-//VOID\r
-//ArmUpdateTranslationTableEntry (\r
-// IN VOID *TranslationTableEntry // R0\r
-// IN VOID *MVA // R1\r
-// );\r
- RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r
- mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r
- dsb\r
- mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r
- mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
- dsb\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateTlb\r
- mov r0,#0\r
- mcr p15,0,r0,c8,c7,0\r
- mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
- dsb\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadScr\r
- mrc p15, 0, r0, c1, c1, 0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteScr\r
- mcr p15, 0, r0, c1, c1, 0\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadHVBar\r
- mrc p15, 4, r0, c12, c0, 0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteHVBar\r
- mcr p15, 4, r0, c12, c0, 0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadMVBar\r
- mrc p15, 0, r0, c12, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteMVBar\r
- mcr p15, 0, r0, c12, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmCallWFE\r
- wfe\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmCallSEV\r
- sev\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadSctlr\r
- mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteSctlr\r
- mcr p15, 0, r0, c1, c0, 0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCpuActlr\r
- mrc p15, 0, r0, c1, c0, 1\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCpuActlr\r
- mcr p15, 0, r0, c1, c0, 1\r
- dsb\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmGetPhysicalAddressBits\r
- mrc p15, 0, r0, c0, c1, 4 ; MMFR0\r
- and r0, r0, #0xf ; VMSA [3:0]\r
- cmp r0, #5 ; >= 5 implies LPAE support\r
- movlt r0, #32 ; 32 bits if no LPAE\r
- movge r0, #40 ; 40 bits if LPAE\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
-\r
-//------------------------------------------------------------------------------\r
-\r
- RVCT_ASM_EXPORT ArmIsMpCore\r
- mrc p15,0,R0,c0,c0,5\r
- // Get Multiprocessing extension (bit31) & U bit (bit30)\r
- and R0, R0, #0xC0000000\r
- // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r
- cmp R0, #0x80000000\r
- moveq R0, #1\r
- movne R0, #0\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableAsynchronousAbort\r
- cpsie a\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableAsynchronousAbort\r
- cpsid a\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableIrq\r
- cpsie i\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableIrq\r
- cpsid i\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableFiq\r
- cpsie f\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableFiq\r
- cpsid f\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableInterrupts\r
- cpsie if\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableInterrupts\r
- cpsid if\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmReadIdMmfr4\r
- mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register\r
- bx LR\r
-\r
-// UINTN\r
-// ReadCCSIDR (\r
-// IN UINT32 CSSELR\r
-// )\r
- RVCT_ASM_EXPORT ReadCCSIDR\r
- mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r
- isb\r
- mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r
- bx lr\r
-\r
-// UINT32\r
-// ReadCCSIDR2 (\r
-// IN UINT32 CSSELR\r
-// )\r
- RVCT_ASM_EXPORT ReadCCSIDR2\r
- mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r
- isb\r
- mrc p15,1,r0,c0,c0,2 ; Read current CP15 Cache Size ID Register (CCSIDR2)\r
- bx lr\r
-\r
-// UINT32\r
-// ReadCLIDR (\r
-// IN UINT32 CSSELR\r
-// )\r
- RVCT_ASM_EXPORT ReadCLIDR\r
- mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadNsacr\r
- mrc p15, 0, r0, c1, c1, 2\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteNsacr\r
- mcr p15, 0, r0, c1, c1, 2\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
- PRESERVE8\r
-\r
- RVCT_ASM_EXPORT ArmReadCntFrq\r
- mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntFrq\r
- mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntPct\r
- mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntkCtl\r
- mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntkCtl\r
- mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntpTval\r
- mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntpTval\r
- mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntpCtl\r
- mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntpCtl\r
- mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvTval\r
- mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntvTval\r
- mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvCtl\r
- mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntvCtl\r
- mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvCt\r
- mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntpCval\r
- mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntpCval\r
- mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvCval\r
- mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntvCval\r
- mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadCntvOff\r
- mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteCntvOff\r
- mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
- PRESERVE8\r
-\r
-DC_ON EQU ( 0x1:SHL:2 )\r
-IC_ON EQU ( 0x1:SHL:12 )\r
-CTRL_M_BIT EQU (1 << 0)\r
-CTRL_C_BIT EQU (1 << 2)\r
-CTRL_B_BIT EQU (1 << 7)\r
-CTRL_I_BIT EQU (1 << 12)\r
-\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA\r
- mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU\r
- mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA\r
- mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay\r
- mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
- mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay\r
- mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r
- bx lr\r
-\r
-\r
- RVCT_ASM_EXPORT ArmInvalidateInstructionCache\r
- mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableMmu\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableMmu\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
-\r
- mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r
- mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableCachesAndMmu\r
- mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
- bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
- bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
- bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r
- mcr p15, 0, r0, c1, c0, 0 ; Write control register\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmMmuEnabled\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- and R0,R0,#1\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableDataCache\r
- ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableDataCache\r
- ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableInstructionCache\r
- ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableInstructionCache\r
- ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
- BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableSWPInstruction\r
- mrc p15, 0, r0, c1, c0, 0\r
- orr r0, r0, #0x00000400\r
- mcr p15, 0, r0, c1, c0, 0\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmEnableBranchPrediction\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr r0, r0, #0x00000800 ;\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDisableBranchPrediction\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00000800 ;\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- dsb\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmSetLowVectors\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00002000 ; clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmSetHighVectors\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- orr r0, r0, #0x00002000 ; Set V bit\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmV7AllDataCachesOperation\r
- stmfd SP!,{r4-r12, LR}\r
- mov R1, R0 ; Save Function call in R1\r
- mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
- ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r
- mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r
- beq Finished\r
- mov R10, #0\r
-\r
-Loop1\r
- add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
- mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
- and R12, R12, #7 ; get those 3 bits alone\r
- cmp R12, #2\r
- blt Skip ; no cache or only instruction cache at this level\r
- mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
- isb ; isb to sync the change to the CacheSizeID reg\r
- mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
- and R2, R12, #&7 ; extract the line length field\r
- add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
- ldr R4, =0x3FF\r
- ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
- clz R5, R4 ; R5 is the bit position of the way size increment\r
- ldr R7, =0x00007FFF\r
- ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
-\r
-Loop2\r
- mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
-\r
-Loop3\r
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
- orr R0, R0, R7, LSL R2 ; factor in the index number\r
-\r
- blx R1\r
-\r
- subs R9, R9, #1 ; decrement the way number\r
- bge Loop3\r
- subs R7, R7, #1 ; decrement the index\r
- bge Loop2\r
-Skip\r
- add R10, R10, #2 ; increment the cache number\r
- cmp R3, R10\r
- bgt Loop1\r
-\r
-Finished\r
- dsb\r
- ldmfd SP!, {r4-r12, lr}\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDataMemoryBarrier\r
- dmb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmDataSynchronizationBarrier\r
- dsb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier\r
- isb\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmReadVBar\r
- // Set the Address of the Vector Table in the VBAR register\r
- mrc p15, 0, r0, c12, c0, 0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteVBar\r
- // Set the Address of the Vector Table in the VBAR register\r
- mcr p15, 0, r0, c12, c0, 0\r
- // Ensure the SCTLR.V bit is clear\r
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00002000 ; clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
- isb\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmEnableVFP\r
- // Read CPACR (Coprocessor Access Control Register)\r
- mrc p15, 0, r0, c1, c0, 2\r
- // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
- orr r0, r0, #0x00f00000\r
- // Write back CPACR (Coprocessor Access Control Register)\r
- mcr p15, 0, r0, c1, c0, 2\r
- isb\r
- // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
- mov r0, #0x40000000\r
- mcr p10,#0x7,r0,c8,c0,#0\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmCallWFI\r
- wfi\r
- bx lr\r
-\r
-//Note: Return 0 in Uniprocessor implementation\r
- RVCT_ASM_EXPORT ArmReadCbar\r
- mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadMpidr\r
- mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadTpidrurw\r
- mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmWriteTpidrurw\r
- mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmIsArchTimerImplemented\r
- mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
- and r0, r0, #0x000F0000\r
- bx lr\r
-\r
- RVCT_ASM_EXPORT ArmReadIdPfr1\r
- mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
- bx lr\r
-\r
- END\r
Arm/ArmV7Support.S | GCC\r
Arm/ArmV7ArchTimerSupport.S | GCC\r
\r
- Arm/ArmLibSupport.asm | RVCT\r
- Arm/ArmLibSupportV7.asm | RVCT\r
- Arm/ArmV7Support.asm | RVCT\r
- Arm/ArmV7ArchTimerSupport.asm | RVCT\r
-\r
[Sources.AARCH64]\r
AArch64/AArch64Lib.h\r
AArch64/AArch64Lib.c\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2016, Linaro Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
-\r
-//------------------------------------------------------------------------------\r
-\r
- RVCT_ASM_EXPORT ArmHasMpExtensions\r
- mrc p15,0,R0,c0,c0,5\r
- // Get Multiprocessing extension (bit31)\r
- lsr R0, R0, #31\r
- bx LR\r
-\r
- RVCT_ASM_EXPORT ArmReadIdMmfr0\r
- mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register\r
- bx lr\r
-\r
- END\r
Arm/ArmMmuLibCore.c\r
Arm/ArmMmuLibUpdate.c\r
Arm/ArmMmuLibV7Support.S |GCC\r
- Arm/ArmMmuLibV7Support.asm |RVCT\r
\r
[Packages]\r
ArmPkg/ArmPkg.dec\r
+++ /dev/null
-//\r
-// Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
- RVCT_ASM_EXPORT ArmCallSmc\r
- push {r4-r8}\r
- // r0 will be popped just after the SMC call\r
- push {r0}\r
-\r
- // Load the SMC arguments values into the appropriate registers\r
- ldr r7, [r0, #28]\r
- ldr r6, [r0, #24]\r
- ldr r5, [r0, #20]\r
- ldr r4, [r0, #16]\r
- ldr r3, [r0, #12]\r
- ldr r2, [r0, #8]\r
- ldr r1, [r0, #4]\r
- ldr r0, [r0, #0]\r
-\r
- smc #0\r
-\r
- // Pop the ARM_SMC_ARGS structure address from the stack into r8\r
- pop {r8}\r
-\r
- // Load the SMC returned values into the appropriate registers\r
- // A SMC call can return up to 4 values - we do not need to store back r4-r7.\r
- str r3, [r8, #12]\r
- str r2, [r8, #8]\r
- str r1, [r8, #4]\r
- str r0, [r8, #0]\r
-\r
- mov r0, r8\r
-\r
- // Restore the registers r4-r8\r
- pop {r4-r8}\r
-\r
- bx lr\r
-\r
- END\r
LIBRARY_CLASS = ArmSmcLib\r
\r
[Sources.ARM]\r
- Arm/ArmSmc.asm | RVCT\r
Arm/ArmSmc.S | GCC\r
\r
[Sources.AARCH64]\r
[Packages]\r
MdePkg/MdePkg.dec\r
ArmPkg/ArmPkg.dec\r
-\r
-[BuildOptions]\r
- RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu 7-A.security\r
+++ /dev/null
-//\r
-// Copyright (c) 2016 - 2020, ARM Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
- RVCT_ASM_EXPORT ArmCallSvc\r
- // r0 will be popped just after the SVC call\r
- push {r0, r4-r8}\r
-\r
- // Load the SVC arguments values into the appropriate registers\r
- ldm r0, {r0-r7}\r
-\r
- svc #0\r
- // Prevent speculative execution beyond svc instruction\r
- dsb nsh\r
- isb\r
-\r
- // Load the ARM_SVC_ARGS structure address from the stack into r8\r
- ldr r8, [sp]\r
-\r
- // Load the SVC returned values into the appropriate registers\r
- // A SVC call can return up to 4 values - we do not need to store back r4-r7.\r
- stm r8, {r0-r3}\r
-\r
- mov r0, r8\r
-\r
- // Restore the registers r4-r8\r
- pop {r1, r4-r8}\r
- bx lr\r
-\r
- END\r
LIBRARY_CLASS = ArmSvcLib\r
\r
[Sources.ARM]\r
- Arm/ArmSvc.asm | RVCT\r
Arm/ArmSvc.S | GCC\r
\r
[Sources.AARCH64]\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
-;\r
-;UINT32\r
-;EFIAPI\r
-;__aeabi_lasr (\r
-; IN UINT32 Dividen\r
-; IN UINT32 Divisor\r
-; );\r
-;\r
- RVCT_ASM_EXPORT __aeabi_lasr\r
- SUBS r3,r2,#0x20\r
- BPL {pc} + 0x18 ; 0x1c\r
- RSB r3,r2,#0x20\r
- LSR r0,r0,r2\r
- ORR r0,r0,r1,LSL r3\r
- ASR r1,r1,r2\r
- BX lr\r
- ASR r0,r1,r3\r
- ASR r1,r1,#31\r
- BX lr\r
-\r
- END\r
-\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
-;\r
-;VOID\r
-;EFIAPI\r
-;__aeabi_llsl (\r
-; IN VOID *Destination,\r
-; IN VOID *Source,\r
-; IN UINT32 Size\r
-; );\r
-;\r
-\r
- RVCT_ASM_EXPORT __aeabi_llsl\r
- SUBS r3,r2,#0x20\r
- BPL {pc} + 0x18 ; 0x1c\r
- RSB r3,r2,#0x20\r
- LSL r1,r1,r2\r
- ORR r1,r1,r0,LSR r3\r
- LSL r0,r0,r2\r
- BX lr\r
- LSL r1,r0,r3\r
- MOV r0,#0\r
- BX lr\r
-\r
- END\r
-\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
-;\r
-;VOID\r
-;EFIAPI\r
-;__aeabi_memmove (\r
-; IN VOID *Destination,\r
-; IN CONST VOID *Source,\r
-; IN UINT32 Size\r
-; );\r
-;\r
- RVCT_ASM_EXPORT __aeabi_memmove\r
- CMP r2, #0\r
- BXEQ lr\r
- CMP r0, r1\r
- BXEQ lr\r
- BHI memmove_backward\r
-\r
-memmove_forward\r
- LDRB r3, [r1], #1\r
- STRB r3, [r0], #1\r
- SUBS r2, r2, #1\r
- BNE memmove_forward\r
- BX lr\r
-\r
-memmove_backward\r
- add r0, r2\r
- add r1, r2\r
-memmove_backward_loop\r
- LDRB r3, [r1, #-1]!\r
- STRB r3, [r0, #-1]!\r
- SUBS r2, r2, #1\r
- BNE memmove_backward_loop\r
- BX lr\r
-\r
- END\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
- EXPORT __ARM_ll_mullu\r
- EXPORT __aeabi_lmul\r
-\r
- AREA Math, CODE, READONLY\r
-\r
-;\r
-;INT64\r
-;EFIAPI\r
-;__aeabi_lmul (\r
-; IN INT64 Multiplicand\r
-; IN INT32 Multiplier\r
-; );\r
-;\r
-__ARM_ll_mullu\r
- mov r3, #0\r
-// Make upper part of INT64 Multiplier 0 and use __aeabi_lmul\r
-\r
-;\r
-;INT64\r
-;EFIAPI\r
-;__aeabi_lmul (\r
-; IN INT64 Multiplicand\r
-; IN INT64 Multiplier\r
-; );\r
-;\r
-__aeabi_lmul\r
- stmdb sp!, {lr}\r
- mov lr, r0\r
- umull r0, ip, r2, lr\r
- mla r1, r2, r1, ip\r
- mla r1, r3, lr, r1\r
- ldmia sp!, {pc}\r
-\r
- END\r
+++ /dev/null
-///------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
- RVCT_ASM_EXPORT __ARM_switch8\r
- LDRB r12,[lr,#-1]\r
- CMP r3,r12\r
- LDRBCC r3,[lr,r3]\r
- LDRBCS r3,[lr,r12]\r
- ADD r12,lr,r3,LSL #1\r
- BX r12\r
-\r
- END\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
-;\r
-;UINT32\r
-;EFIAPI\r
-;__aeabi_uread4 (\r
-; IN VOID *Pointer\r
-; );\r
-;\r
- RVCT_ASM_EXPORT __aeabi_uread4\r
- ldrb r1, [r0]\r
- ldrb r2, [r0, #1]\r
- ldrb r3, [r0, #2]\r
- ldrb r0, [r0, #3]\r
- orr r1, r1, r2, lsl #8\r
- orr r1, r1, r3, lsl #16\r
- orr r0, r1, r0, lsl #24\r
- bx lr\r
-\r
-;\r
-;UINT64\r
-;EFIAPI\r
-;__aeabi_uread8 (\r
-; IN VOID *Pointer\r
-; );\r
-;\r
- RVCT_ASM_EXPORT __aeabi_uread8\r
- mov r3, r0\r
-\r
- ldrb r1, [r3]\r
- ldrb r2, [r3, #1]\r
- orr r1, r1, r2, lsl #8\r
- ldrb r2, [r3, #2]\r
- orr r1, r1, r2, lsl #16\r
- ldrb r0, [r3, #3]\r
- orr r0, r1, r0, lsl #24\r
-\r
- ldrb r1, [r3, #4]\r
- ldrb r2, [r3, #5]\r
- orr r1, r1, r2, lsl #8\r
- ldrb r2, [r3, #6]\r
- orr r1, r1, r2, lsl #16\r
- ldrb r2, [r3, #7]\r
- orr r1, r1, r2, lsl #24\r
-\r
- bx lr\r
- END\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-//\r
-// SPDX-License-Identifier: BSD-2-Clause-Patent\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-\r
- INCLUDE AsmMacroExport.inc\r
-\r
-;\r
-;UINT32\r
-;EFIAPI\r
-;__aeabi_uwrite4 (\r
-; IN UINT32 Data,\r
-; IN VOID *Pointer\r
-; );\r
-;\r
-;\r
- RVCT_ASM_EXPORT __aeabi_uwrite4\r
- mov r2, r0, lsr #8\r
- strb r0, [r1]\r
- strb r2, [r1, #1]\r
- mov r2, r0, lsr #16\r
- strb r2, [r1, #2]\r
- mov r2, r0, lsr #24\r
- strb r2, [r1, #3]\r
- bx lr\r
-\r
-;\r
-;UINT64\r
-;EFIAPI\r
-;__aeabi_uwrite8 (\r
-; IN UINT64 Data, //r0-r1\r
-; IN VOID *Pointer //r2\r
-; );\r
-;\r
-;\r
- RVCT_ASM_EXPORT __aeabi_uwrite8\r
- mov r3, r0, lsr #8\r
- strb r0, [r2]\r
- strb r3, [r2, #1]\r
- mov r3, r0, lsr #16\r
- strb r3, [r2, #2]\r
- mov r3, r0, lsr #24\r
- strb r3, [r2, #3]\r
-\r
- mov r3, r1, lsr #8\r
- strb r1, [r2, #4]\r
- strb r3, [r2, #5]\r
- mov r3, r1, lsr #16\r
- strb r3, [r2, #6]\r
- mov r3, r1, lsr #24\r
- strb r3, [r2, #7]\r
- bx lr\r
-\r
- END\r
-\r
LIBRARY_CLASS = CompilerIntrinsicsLib\r
\r
[Sources]\r
- memcpy.c | RVCT\r
- memset.c | RVCT\r
-\r
memcpy.c | GCC\r
memset.c | GCC\r
\r
memmove_ms.c | MSFT\r
\r
[Sources.ARM]\r
- Arm/mullu.asm | RVCT\r
- Arm/switch.asm | RVCT\r
- Arm/llsr.asm | RVCT\r
- Arm/memmove.asm | RVCT\r
- Arm/uread.asm | RVCT\r
- Arm/uwrite.asm | RVCT\r
- Arm/lasr.asm | RVCT\r
- Arm/llsl.asm | RVCT\r
- Arm/div.asm | RVCT\r
- Arm/uldiv.asm | RVCT\r
- Arm/ldivmod.asm | RVCT\r
-\r
Arm/ashrdi3.S | GCC\r
Arm/ashldi3.S | GCC\r
Arm/div.S | GCC\r
projects / mirror_edk2.git / commitdiff