InitializeListHead (&AtaDevice->AtaTaskList);\r
InitializeListHead (&AtaDevice->AtaSubTaskList);\r
\r
+ //\r
+ // Report Status Code to indicate the ATA device will be enabled\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_PC_ENABLE),\r
+ AtaBusDriverData->ParentDevicePath\r
+ );\r
+\r
//\r
// Try to identify the ATA device via the ATA pass through command.\r
//\r
return Status;\r
}\r
\r
+ //\r
+ // Report Status Code to indicate ATA bus starts\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_PC_INIT),\r
+ ParentDevicePath\r
+ );\r
+\r
Status = gBS->OpenProtocol (\r
Controller,\r
&gEfiAtaPassThruProtocolGuid,\r
}\r
}\r
\r
+ //\r
+ // Report Status Code to indicate detecting devices on bus\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_PC_DETECT),\r
+ ParentDevicePath\r
+ );\r
+\r
if (RemainingDevicePath == NULL) {\r
Port = 0xFFFF;\r
while (TRUE) {\r
#include <Library/DevicePathLib.h>\r
#include <Library/UefiRuntimeServicesTableLib.h>\r
#include <Library/TimerLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
\r
#include <IndustryStandard/Atapi.h>\r
\r
UefiDriverEntryPoint\r
DebugLib\r
TimerLib\r
+ ReportStatusCodeLib\r
\r
[Guids]\r
gEfiDiskInfoIdeInterfaceGuid # CONSUMES ## GUID\r
\r
AtaPassThru = AtaDevice->AtaBusDriverData->AtaPassThru;\r
\r
+ //\r
+ // Report Status Code to indicate reset happens\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_PC_RESET),\r
+ AtaDevice->AtaBusDriverData->ParentDevicePath\r
+ );\r
+\r
return AtaPassThru->ResetDevice (\r
AtaPassThru,\r
AtaDevice->Port,\r
EFI_STATUS Status;\r
UINT32 DbgCtrlStatus;\r
\r
+ Ehc = EHC_FROM_THIS (This);\r
+\r
+ if (Ehc->DevicePath != NULL) {\r
+ //\r
+ // Report Status Code to indicate reset happens\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_USB | EFI_IOB_PC_RESET),\r
+ Ehc->DevicePath\r
+ );\r
+ }\r
+\r
OldTpl = gBS->RaiseTPL (EHC_TPL);\r
- Ehc = EHC_FROM_THIS (This);\r
\r
switch (Attributes) {\r
case EFI_USB_HC_RESET_GLOBAL:\r
**/\r
USB2_HC_DEV *\r
EhcCreateUsb2Hc (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT64 OriginalPciAttributes\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN UINT64 OriginalPciAttributes\r
)\r
{\r
USB2_HC_DEV *Ehc;\r
Ehc->Usb2Hc.MinorRevision = 0x0;\r
\r
Ehc->PciIo = PciIo;\r
+ Ehc->DevicePath = DevicePath;\r
Ehc->OriginalPciAttributes = OriginalPciAttributes;\r
\r
InitializeListHead (&Ehc->AsyncIntTransfers);\r
UINTN EhciDeviceNumber;\r
UINTN EhciFunctionNumber;\r
UINT32 State;\r
+ EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;\r
\r
//\r
// Open the PciIo Protocol, then enable the USB host controller\r
return Status;\r
}\r
\r
+ //\r
+ // Open Device Path Protocol for on USB host controller\r
+ //\r
+ HcDevicePath = NULL;\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **) &HcDevicePath,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+ );\r
+\r
PciAttributesSaved = FALSE;\r
//\r
// Save original PCI attributes\r
//\r
// Create then install USB2_HC_PROTOCOL\r
//\r
- Ehc = EhcCreateUsb2Hc (PciIo, OriginalPciAttributes);\r
+ Ehc = EhcCreateUsb2Hc (PciIo, HcDevicePath, OriginalPciAttributes);\r
\r
if (Ehc == NULL) {\r
DEBUG ((EFI_D_ERROR, "EhcDriverBindingStart: failed to create USB2_HC\n"));\r
#include <Library/BaseLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
\r
#include <IndustryStandard/Pci.h>\r
\r
EFI_USB2_HC_PROTOCOL Usb2Hc;\r
\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
UINT64 OriginalPciAttributes;\r
USBHC_MEM_POOL *MemPool;\r
\r
# This way avoids the control transfer on a shared port between EHCI and companion host\r
# controller when UHCI gets attached earlier than EHCI and a USB 2.0 device inserts.\r
#\r
-# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
BaseMemoryLib\r
DebugLib\r
PcdLib\r
+ ReportStatusCodeLib\r
\r
[Guids]\r
gEfiEventExitBootServicesGuid ## PRODUCES ## Event\r
PCI Root Bridges. So it means platform needs install PCI Root Bridge IO protocol for each\r
PCI Root Bus and install PCI Host Bridge Resource Allocation Protocol.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;\r
\r
//\r
// Check RemainingDevicePath validation\r
\r
gFullEnumeration = (BOOLEAN) ((SearchHostBridgeHandle (Controller) ? FALSE : TRUE));\r
\r
+ //\r
+ // Open Device Path Protocol for PCI root bridge\r
+ //\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **) &ParentDevicePath,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+ ); \r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Report Status Code to indicate PCI bus starts\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_PCI | EFI_IOB_PC_INIT),\r
+ ParentDevicePath\r
+ );\r
+\r
//\r
// Enumerate the entire host bridge\r
// After enumeration, a database that records all the device information will be created\r
/** @file\r
PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
RootBridgeHandle = Temp->Handle;\r
\r
if (Operation == EfiPciHotPlugRequestAdd) {\r
+ //\r
+ // Report Status Code to indicate hot plug happens\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_PCI | EFI_IOB_PC_HOTPLUG),\r
+ Temp->DevicePath\r
+ );\r
\r
if (NumberOfChildren != NULL) {\r
*NumberOfChildren = 0;\r
\r
The UHCI driver model and HC protocol routines.\r
\r
-Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
return EFI_UNSUPPORTED;\r
}\r
\r
- Uhc = UHC_FROM_USB2_HC_PROTO (This);\r
+ Uhc = UHC_FROM_USB2_HC_PROTO (This);\r
+\r
+ if (Uhc->DevicePath != NULL) {\r
+ //\r
+ // Report Status Code to indicate reset happens\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_USB | EFI_IOB_PC_RESET),\r
+ Uhc->DevicePath\r
+ );\r
+ }\r
\r
OldTpl = gBS->RaiseTPL (UHCI_TPL);\r
\r
**/\r
USB_HC_DEV *\r
UhciAllocateDev (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT64 OriginalPciAttributes\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN UINT64 OriginalPciAttributes\r
)\r
{\r
USB_HC_DEV *Uhc;\r
Uhc->Usb2Hc.MinorRevision = 0x1;\r
\r
Uhc->PciIo = PciIo;\r
+ Uhc->DevicePath = DevicePath;\r
Uhc->OriginalPciAttributes = OriginalPciAttributes;\r
Uhc->MemPool = UsbHcInitMemPool (PciIo, TRUE, 0);\r
\r
UINT64 Supports;\r
UINT64 OriginalPciAttributes;\r
BOOLEAN PciAttributesSaved;\r
+ EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;\r
\r
//\r
// Open PCIIO, then enable the EHC device and turn off emulation\r
return Status;\r
}\r
\r
+ //\r
+ // Open Device Path Protocol for on USB host controller\r
+ //\r
+ HcDevicePath = NULL;\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **) &HcDevicePath,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+ );\r
+\r
PciAttributesSaved = FALSE;\r
//\r
// Save original PCI attributes\r
goto CLOSE_PCIIO;\r
}\r
\r
- Uhc = UhciAllocateDev (PciIo, OriginalPciAttributes);\r
+ Uhc = UhciAllocateDev (PciIo, HcDevicePath, OriginalPciAttributes);\r
\r
if (Uhc == NULL) {\r
Status = EFI_OUT_OF_RESOURCES;\r
\r
The definition for UHCI driver model and HC protocol routines.\r
\r
-Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <Library/BaseLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
\r
#include <IndustryStandard/Pci.h>\r
\r
UINT32 Signature;\r
EFI_USB2_HC_PROTOCOL Usb2Hc;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
UINT64 OriginalPciAttributes;\r
\r
//\r
# It implements the interfaces of monitoring the status of all ports and transferring\r
# Control, Bulk, Interrupt and Isochronous requests to Usb1.x device\r
#\r
-# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
BaseMemoryLib\r
DebugLib\r
PcdLib\r
+ ReportStatusCodeLib\r
\r
[Guids]\r
gEfiEventExitBootServicesGuid ## PRODUCES ## Event\r
)
{
USB_XHCI_INSTANCE *Xhc;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
-
- OldTpl = gBS->RaiseTPL (XHC_TPL);
-
- Xhc = XHC_FROM_THIS (This);
-
- switch (Attributes) {
- case EFI_USB_HC_RESET_GLOBAL:
- //
+ EFI_STATUS Status;\r
+ EFI_TPL OldTpl;\r
+\r
+ Xhc = XHC_FROM_THIS (This);\r
+ \r
+ if (Xhc->DevicePath != NULL) {\r
+ //\r
+ // Report Status Code to indicate reset happens\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_USB | EFI_IOB_PC_RESET),\r
+ Xhc->DevicePath\r
+ );\r
+ } \r
+\r
+ OldTpl = gBS->RaiseTPL (XHC_TPL);\r
+\r
+ switch (Attributes) {\r
+ case EFI_USB_HC_RESET_GLOBAL:\r
+ //\r
// Flow through, same behavior as Host Controller Reset
//
case EFI_USB_HC_RESET_HOST_CONTROLLER:
@return The allocated and initialized USB_XHCI_INSTANCE structure if created,
otherwise NULL.
-**/
-USB_XHCI_INSTANCE*
-XhcCreateUsbHc (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT64 OriginalPciAttributes
- )
-{
- USB_XHCI_INSTANCE *Xhc;
+**/\r
+USB_XHCI_INSTANCE*\r
+XhcCreateUsbHc (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN UINT64 OriginalPciAttributes\r
+ )\r
+{\r
+ USB_XHCI_INSTANCE *Xhc;\r
EFI_STATUS Status;
UINT32 PageSize;
UINT16 ExtCapReg;
//
// Initialize private data structure
- //
- Xhc->Signature = XHCI_INSTANCE_SIG;
- Xhc->PciIo = PciIo;
- Xhc->OriginalPciAttributes = OriginalPciAttributes;
- CopyMem (&Xhc->Usb2Hc, &gXhciUsb2HcTemplate, sizeof (EFI_USB2_HC_PROTOCOL));
-
+ //\r
+ Xhc->Signature = XHCI_INSTANCE_SIG;\r
+ Xhc->PciIo = PciIo;\r
+ Xhc->DevicePath = DevicePath;\r
+ Xhc->OriginalPciAttributes = OriginalPciAttributes;\r
+ CopyMem (&Xhc->Usb2Hc, &gXhciUsb2HcTemplate, sizeof (EFI_USB2_HC_PROTOCOL));\r
+\r
InitializeListHead (&Xhc->AsyncIntTransfers);
//
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 Supports;
- UINT64 OriginalPciAttributes;
- BOOLEAN PciAttributesSaved;
- USB_XHCI_INSTANCE *Xhc;
-
- //
- // Open the PciIo Protocol, then enable the USB host controller
+ UINT64 OriginalPciAttributes;\r
+ BOOLEAN PciAttributesSaved;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;\r
+\r
+ //\r
+ // Open the PciIo Protocol, then enable the USB host controller\r
//
Status = gBS->OpenProtocol (
Controller,
);
if (EFI_ERROR (Status)) {
- return Status;
- }
-
- PciAttributesSaved = FALSE;
- //
- // Save original PCI attributes
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Open Device Path Protocol for on USB host controller\r
+ //\r
+ HcDevicePath = NULL;\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **) &HcDevicePath,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+ );\r
+\r
+ PciAttributesSaved = FALSE;\r
+ //\r
+ // Save original PCI attributes\r
//
Status = PciIo->Attributes (
PciIo,
goto CLOSE_PCIIO;
}
- //
- // Create then install USB2_HC_PROTOCOL
- //
- Xhc = XhcCreateUsbHc (PciIo, OriginalPciAttributes);
-
- if (Xhc == NULL) {
- DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));
+ //\r
+ // Create then install USB2_HC_PROTOCOL\r
+ //\r
+ Xhc = XhcCreateUsbHc (PciIo, HcDevicePath, OriginalPciAttributes);\r
+\r
+ if (Xhc == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));\r
return EFI_OUT_OF_RESOURCES;
}
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/DebugLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
\r
#include <IndustryStandard/Pci.h>\r
\r
# It implements the interfaces of monitoring the status of all ports and transferring\r
# Control, Bulk, Interrupt and Isochronous requests to those attached usb LS/FS/HS/SS devices.\r
#\r
-# Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
UefiDriverEntryPoint\r
BaseMemoryLib\r
DebugLib\r
+ ReportStatusCodeLib\r
\r
[Guids]\r
gEfiEventExitBootServicesGuid ## PRODUCES ## Event\r
SCSI Bus driver that layers on every SCSI Pass Thru and\r
Extended SCSI Pass Thru protocol in the system.\r
\r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
return DevicePathStatus;\r
}\r
\r
+ //\r
+ // Report Status Code to indicate SCSI bus starts\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_SCSI | EFI_IOB_PC_INIT),\r
+ ParentDevicePath\r
+ ); \r
+\r
//\r
// To keep backward compatibility, UEFI ExtPassThru Protocol is supported as well as \r
// EFI PassThru Protocol. From priority perspective, ExtPassThru Protocol is firstly\r
ScsiBusDev = SCSI_BUS_CONTROLLER_DEVICE_FROM_THIS (BusIdentify);\r
}\r
\r
+ //\r
+ // Report Status Code to indicate detecting devices on bus\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_SCSI | EFI_IOB_PC_DETECT),\r
+ ParentDevicePath\r
+ );\r
+\r
Lun = 0;\r
if (RemainingDevicePath == NULL) {\r
//\r
\r
ScsiIoDevice = SCSI_IO_DEV_FROM_THIS (This);\r
\r
+ //\r
+ // Report Status Code to indicate reset happens\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_PC_RESET),\r
+ ScsiIoDevice->ScsiBusDeviceData->DevicePath\r
+ );\r
+\r
if (ScsiIoDevice->ExtScsiSupport){\r
return ScsiIoDevice->ExtScsiPassThru->ResetChannel (ScsiIoDevice->ExtScsiPassThru);\r
} else {\r
UINT8 Target[TARGET_MAX_BYTES];\r
\r
ScsiIoDevice = SCSI_IO_DEV_FROM_THIS (This);\r
+\r
+ //\r
+ // Report Status Code to indicate reset happens\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_PC_RESET),\r
+ ScsiIoDevice->ScsiBusDeviceData->DevicePath\r
+ );\r
+ \r
CopyMem (Target,&ScsiIoDevice->Pun, TARGET_MAX_BYTES);\r
\r
\r
}\r
\r
ScsiIoDevice->Signature = SCSI_IO_DEV_SIGNATURE;\r
+ ScsiIoDevice->ScsiBusDeviceData = ScsiBusDev;\r
CopyMem(&ScsiIoDevice->Pun, TargetId, TARGET_MAX_BYTES);\r
ScsiIoDevice->Lun = Lun;\r
\r
ScsiIoDevice->ScsiIo.ResetDevice = ScsiResetDevice;\r
ScsiIoDevice->ScsiIo.ExecuteScsiCommand = ScsiExecuteSCSICommand;\r
\r
+ //\r
+ // Report Status Code here since the new SCSI device will be discovered\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_SCSI | EFI_IOB_PC_ENABLE),\r
+ ScsiBusDev->DevicePath\r
+ );\r
+\r
if (!DiscoverScsiDevice (ScsiIoDevice)) {\r
Status = EFI_OUT_OF_RESOURCES;\r
goto ErrorExit;\r
/** @file\r
Header file for SCSI Bus Driver.\r
\r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <Library/UefiScsiLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
\r
#include <IndustryStandard/Scsi.h>\r
\r
VOID *Data2;\r
} SCSI_EVENT_DATA;\r
\r
-\r
-typedef struct {\r
- UINT32 Signature;\r
- EFI_HANDLE Handle;\r
- EFI_SCSI_IO_PROTOCOL ScsiIo;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
- BOOLEAN ExtScsiSupport; \r
- EFI_SCSI_PASS_THRU_PROTOCOL *ScsiPassThru;\r
- EFI_EXT_SCSI_PASS_THRU_PROTOCOL *ExtScsiPassThru;\r
- SCSI_TARGET_ID Pun;\r
- UINT64 Lun;\r
- UINT8 ScsiDeviceType;\r
- UINT8 ScsiVersion;\r
- BOOLEAN RemovableDevice;\r
-} SCSI_IO_DEV;\r
-\r
-#define SCSI_IO_DEV_FROM_THIS(a) CR (a, SCSI_IO_DEV, ScsiIo, SCSI_IO_DEV_SIGNATURE)\r
-\r
//\r
// SCSI Bus Controller device strcuture\r
//\r
+#define SCSI_BUS_DEVICE_SIGNATURE SIGNATURE_32 ('s', 'c', 's', 'i')\r
\r
//\r
// The ScsiBusProtocol is just used to locate ScsiBusDev\r
UINT64 Reserved;\r
} EFI_SCSI_BUS_PROTOCOL;\r
\r
-#define SCSI_BUS_DEVICE_SIGNATURE SIGNATURE_32 ('s', 'c', 's', 'i')\r
-\r
-\r
typedef struct _SCSI_BUS_DEVICE {\r
UINTN Signature;\r
EFI_SCSI_BUS_PROTOCOL BusIdentify;\r
\r
#define SCSI_BUS_CONTROLLER_DEVICE_FROM_THIS(a) CR (a, SCSI_BUS_DEVICE, BusIdentify, SCSI_BUS_DEVICE_SIGNATURE)\r
\r
+typedef struct {\r
+ UINT32 Signature;\r
+ EFI_HANDLE Handle;\r
+ EFI_SCSI_IO_PROTOCOL ScsiIo;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ BOOLEAN ExtScsiSupport; \r
+ EFI_SCSI_PASS_THRU_PROTOCOL *ScsiPassThru;\r
+ EFI_EXT_SCSI_PASS_THRU_PROTOCOL *ExtScsiPassThru;\r
+ SCSI_BUS_DEVICE *ScsiBusDeviceData;\r
+ SCSI_TARGET_ID Pun;\r
+ UINT64 Lun;\r
+ UINT8 ScsiDeviceType;\r
+ UINT8 ScsiVersion;\r
+ BOOLEAN RemovableDevice;\r
+} SCSI_IO_DEV;\r
+\r
+#define SCSI_IO_DEV_FROM_THIS(a) CR (a, SCSI_IO_DEV, ScsiIo, SCSI_IO_DEV_SIGNATURE)\r
+\r
//\r
// Global Variables\r
//\r
# each of them. After this the driver installs the Device Path Protocol and SCSI I/O Protocol on\r
# these handles.\r
# \r
-# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
UefiDriverEntryPoint\r
DebugLib\r
MemoryAllocationLib\r
+ ReportStatusCodeLib\r
\r
\r
[Protocols]\r
\r
Usb Bus Driver Binding and Bus IO Protocol.\r
\r
-Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
RootIf->Signature = USB_INTERFACE_SIGNATURE;\r
RootIf->Device = RootHub;\r
RootIf->DevicePath = UsbBus->DevicePath;\r
-\r
+ \r
+ //\r
+ // Report Status Code here since we will enumerate the USB devices\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_USB | EFI_IOB_PC_DETECT),\r
+ UsbBus->DevicePath\r
+ );\r
+ \r
Status = mUsbRootHubApi.Init (RootIf);\r
\r
if (EFI_ERROR (Status)) {\r
{\r
EFI_USB_BUS_PROTOCOL *UsbBusId;\r
EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;\r
+\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **) &ParentDevicePath,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Report Status Code here since we will initialize the host controller\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_USB | EFI_IOB_PC_INIT),\r
+ ParentDevicePath\r
+ );\r
\r
//\r
// Locate the USB bus protocol, if it is found, USB bus\r
goto ON_ERROR;\r
}\r
\r
+ //\r
+ // Report Status Code to indicate USB device has been detected by hotplug\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_USB | EFI_IOB_PC_HOTPLUG),\r
+ Bus->DevicePath\r
+ );\r
return EFI_SUCCESS;\r
\r
ON_ERROR:\r
\r
if (!Found) {\r
//\r
+ // Report Status Code to indicate that there is no USB keyboard\r
+ //\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ (EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_NOT_DETECTED)\r
+ );\r
+ //\r
// No interrupt endpoint found, then return unsupported.\r
//\r
Status = EFI_UNSUPPORTED;\r
goto ErrorExit;\r
}\r
\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_PERIPHERAL_KEYBOARD | EFI_P_PC_DETECTED),\r
+ UsbKeyboardDevice->DevicePath\r
+ );\r
+\r
UsbKeyboardDevice->Signature = USB_KB_DEV_SIGNATURE;\r
UsbKeyboardDevice->SimpleInput.Reset = USBKeyboardReset;\r
UsbKeyboardDevice->SimpleInput.ReadKeyStroke = USBKeyboardReadKeyStroke;\r
if (EFI_ERROR (Status)) {\r
goto ErrorExit;\r
}\r
+\r
+ //\r
+ // Report Status Code here since USB mouse will be detected next.\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_PERIPHERAL_MOUSE | EFI_P_PC_PRESENCE_DETECT),\r
+ UsbMouseDevice->DevicePath\r
+ );\r
+\r
//\r
// Get interface & endpoint descriptor\r
//\r
\r
if (!Found) {\r
//\r
+ // Report Status Code to indicate that there is no USB mouse\r
+ //\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,,\r
+ (EFI_PERIPHERAL_MOUSE | EFI_P_EC_NOT_DETECTED)\r
+ );\r
+ //\r
// No interrupt endpoint found, then return unsupported.\r
//\r
Status = EFI_UNSUPPORTED;\r
goto ErrorExit;\r
}\r
\r
+ //\r
+ // Report Status Code here since USB mouse has be detected.\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_PERIPHERAL_MOUSE | EFI_P_PC_DETECTED),\r
+ UsbMouseDevice->DevicePath\r
+ );\r
+\r
Status = InitializeUsbMouseDevice (UsbMouseAbsolutePointerDevice);\r
if (EFI_ERROR (Status)) {\r
//\r
if (EFI_ERROR (Status)) {\r
goto ErrorExit;\r
}\r
+\r
+ //\r
+ // Report Status Code here since USB mouse will be detected next.\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_PERIPHERAL_MOUSE | EFI_P_PC_PRESENCE_DETECT),\r
+ UsbMouseDevice->DevicePath\r
+ );\r
+\r
//\r
// Get interface & endpoint descriptor\r
//\r
\r
if (!Found) {\r
//\r
+ // Report Status Code to indicate that there is no USB mouse\r
+ //\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ (EFI_PERIPHERAL_MOUSE | EFI_P_EC_NOT_DETECTED)\r
+ );\r
+ //\r
// No interrupt endpoint found, then return unsupported.\r
//\r
Status = EFI_UNSUPPORTED;\r
goto ErrorExit;\r
}\r
\r
+ //\r
+ // Report Status Code here since USB mouse has be detected.\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_PERIPHERAL_MOUSE | EFI_P_PC_DETECTED),\r
+ UsbMouseDevice->DevicePath\r
+ );\r
+\r
Status = InitializeUsbMouseDevice (UsbMouseDevice);\r
if (EFI_ERROR (Status)) {\r
//\r
//\r
// Assert if the Architectural Protocols are not present.\r
//\r
- ASSERT_EFI_ERROR (CoreAllEfiServicesAvailable ());\r
+ Status = CoreAllEfiServicesAvailable ();\r
+ if (EFI_ERROR(Status)) {\r
+ //\r
+ // Report Status code that some Architectural Protocols are not present.\r
+ //\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE | EFI_ERROR_MAJOR,\r
+ (EFI_SOFTWARE_DXE_CORE | EFI_SW_DXE_CORE_EC_NO_ARCH)\r
+ ); \r
+ }\r
+ ASSERT_EFI_ERROR (Status);\r
\r
//\r
// Report Status code before transfer control to BDS\r
Last PEIM.\r
Responsibility of this module is to load the DXE Core from a Firmware Volume.\r
\r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
NULL,\r
(VOID **) &S3Resume\r
);\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Report Status code that S3Resume PPI can not be found\r
+ //\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE | EFI_ERROR_MAJOR,\r
+ (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND)\r
+ );\r
+ }\r
ASSERT_EFI_ERROR (Status);\r
\r
Status = S3Resume->S3RestoreConfig2 (S3Resume);\r
ASSERT_EFI_ERROR (Status);\r
} else if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
+ REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_PC_RECOVERY_BEGIN));\r
Status = PeiServicesLocatePpi (\r
&gEfiPeiRecoveryModulePpiGuid,\r
0,\r
NULL,\r
(VOID **) &PeiRecovery\r
);\r
+ //\r
+ // Report Status code the failure of locating Recovery PPI \r
+ //\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE | EFI_ERROR_MAJOR,\r
+ (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_RECOVERY_PPI_NOT_FOUND)\r
+ ); \r
ASSERT_EFI_ERROR (Status);\r
- \r
+ REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_PC_CAPSULE_LOAD));\r
Status = PeiRecovery->LoadRecoveryCapsule (PeiServices, PeiRecovery);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "Load Recovery Capsule Failed.(Status = %r)\n", Status));\r
+ //\r
+ // Report Status code that S3Resume PPI can not be found\r
+ //\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE | EFI_ERROR_MAJOR,\r
+ (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_NO_RECOVERY_CAPSULE)\r
+ );\r
CpuDeadLoop ();\r
}\r
-\r
+ REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_PC_CAPSULE_START));\r
//\r
// Now should have a HOB with the DXE core\r
//\r
if (!EFI_ERROR (Status)) {\r
return ResetPpi->ResetSystem (PeiServices);\r
} \r
+ //\r
+ // Report Status Code that Reset PPI is not available\r
+ //\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ (EFI_SOFTWARE_PEI_CORE | EFI_SW_PS_EC_RESET_NOT_AVAILABLE)\r
+ );\r
return EFI_NOT_AVAILABLE_YET;\r
}\r
\r
Table now contains an item named CalculateCrc32.\r
\r
\r
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_RS_PC_SET_VIRTUAL_ADDRESS_MAP));\r
\r
+ //\r
+ // Report Status Code here since EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event will be signaled.\r
+ //\r
+ REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT));\r
+\r
//\r
// Signal all the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE events.\r
// All runtime events are stored in a list in Runtime AP.\r
/** @file\r
Definitions for data structures used in S3 resume.\r
\r
-Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
#define SMM_S3_RESUME_SMM_32 SIGNATURE_64 ('S','M','M','S','3','_','3','2')\r
#define SMM_S3_RESUME_SMM_64 SIGNATURE_64 ('S','M','M','S','3','_','6','4')\r
\r
+#pragma pack(1)\r
+\r
typedef struct {\r
UINT64 Signature;\r
EFI_PHYSICAL_ADDRESS SmmS3ResumeEntryPoint;\r
\r
typedef struct {\r
UINT16 ReturnCs;\r
+ UINT64 ReturnStatus;\r
EFI_PHYSICAL_ADDRESS ReturnEntryPoint;\r
EFI_PHYSICAL_ADDRESS ReturnStackPointer;\r
EFI_PHYSICAL_ADDRESS AsmTransferControl;\r
IA32_DESCRIPTOR Idtr;\r
} PEI_S3_RESUME_STATE;\r
\r
+#pragma pack()\r
+\r
#define EFI_ACPI_S3_CONTEXT_GUID \\r
{ \\r
0xef98d3a, 0x3e33, 0x497a, {0xa4, 0x1, 0x77, 0xbe, 0x3e, 0xb7, 0x4f, 0x38} \\r
// for that parameter.\r
//\r
Status = S3BootScriptExecute ();\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+\r
+ //\r
+ // Need report status back to S3ResumePeim. \r
+ // If boot script execution is failed, S3ResumePeim wil report the error status code.\r
+ //\r
+ PeiS3ResumeState->ReturnStatus = (UINT64)(UINTN)Status;\r
\r
AsmWbinvd ();\r
\r
//\r
Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));\r
\r
- if ((Facs == NULL) ||\r
- (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||\r
- ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {\r
- CpuDeadLoop();\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
//\r
// We need turn back to S3Resume - install boot script done ppi and report status code on S3resume.\r
//\r
DEBUG ((EFI_D_ERROR, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));\r
PeiS3ResumeState->AsmTransferControl = (EFI_PHYSICAL_ADDRESS)(UINTN)AsmTransferControl32;\r
\r
- //\r
- // more step needed - because relative address is handled differently between X64 and IA32.\r
- //\r
- AsmTransferControl16Address = (UINTN)AsmTransferControl16;\r
- AsmFixAddress16 = (UINT32)AsmTransferControl16Address;\r
- AsmJmpAddr32 = (UINT32)((Facs->FirmwareWakingVector & 0xF) | ((Facs->FirmwareWakingVector & 0xFFFF0) << 12));\r
+ if ((Facs != NULL) &&\r
+ (Facs->Signature == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) &&\r
+ (Facs->FirmwareWakingVector != 0) ) {\r
+ //\r
+ // more step needed - because relative address is handled differently between X64 and IA32.\r
+ //\r
+ AsmTransferControl16Address = (UINTN)AsmTransferControl16;\r
+ AsmFixAddress16 = (UINT32)AsmTransferControl16Address;\r
+ AsmJmpAddr32 = (UINT32)((Facs->FirmwareWakingVector & 0xF) | ((Facs->FirmwareWakingVector & 0xFFFF0) << 12));\r
+ }\r
\r
AsmDisablePaging64 (\r
PeiS3ResumeState->ReturnCs,\r
CpuDeadLoop();\r
return EFI_UNSUPPORTED;\r
}\r
-\r
+ \r
+ //\r
+ // S3ResumePeim does not provide a way to jump back to itself, so resume to OS here directly\r
+ //\r
if (Facs->XFirmwareWakingVector != 0) {\r
//\r
// Switch to native waking vector\r
EFI_STATUS Status;\r
UINTN Size;\r
UINTN CapsuleDataPtr;\r
+ \r
+ //\r
+ // Indicate reset system runtime service is called.\r
+ //\r
+ REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_RS_PC_RESET_SYSTEM));\r
\r
switch (ResetType) {\r
case EfiResetWarm:\r
#include <Library/UefiRuntimeLib.h>\r
#include <Library/UefiRuntimeServicesTableLib.h>\r
#include <Library/ResetSystemLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
\r
/**\r
The driver's entry point.\r
#\r
# This driver implements Reset Architectural Protocol.\r
#\r
-# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials are\r
# licensed and made available under the terms and conditions of the BSD License\r
UefiLib\r
DebugLib\r
BaseLib\r
+ ReportStatusCodeLib\r
\r
\r
[Guids]\r
projects / mirror_edk2.git / commitdiff