Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
\r
///\r
/// EFI SMM Access PPI is used to control the visibility of the SMRAM on the platform.\r
-/// It abstracts the location and characteristics of SMRAM. The expectation is\r
-/// that the north bridge or memory controller would publish this PPI.\r
+/// It abstracts the location and characteristics of SMRAM. The platform should report \r
+/// all MMRAM via PEI_SMM_ACCESS_PPI. The expectation is that the north bridge or \r
+/// memory controller would publish this PPI.\r
/// \r
struct _PEI_SMM_ACCESS_PPI {\r
PEI_SMM_OPEN Open;\r