IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381

In Dispatch mode FSP may consume PPI directly so creating
FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD.
Also Keeps new structure size 8 bytes alignment as other
structures.

Test: Verified on internal platform to boot with this PPI
installed successfully.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644 (file)
index 0000000..5bedb95
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,54 @@
+/** @file\r
+  Header file for FSP-M Arch Config PPI for Dispatch mode\r
+\r
+ @copyright\r
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License which accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_\r
+#define _FSPM_ARCH_CONFIG_PPI_H_\r
+\r
+#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1\r
+\r
+///\r
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.\r
+///\r
+#define FSPM_ARCH_CONFIG_GUID \\r
+  { \\r
+    0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \\r
+  }\r
+\r
+///\r
+/// This PPI provides FSP-M Arch Config PPI.\r
+///\r
+typedef struct {\r
+  ///\r
+  /// Revision of the structure\r
+  ///\r
+  UINT8         Revision;\r
+  UINT8         Reserved[3];\r
+  ///\r
+  /// Pointer to the non-volatile storage (NVS) data buffer.\r
+  /// If it is NULL it indicates the NVS data is not available.\r
+  ///\r
+  VOID          *NvsBufferPtr;\r
+  ///\r
+  /// Size of memory to be reserved by FSP below "top\r
+  /// of low usable memory" for bootloader usage.\r
+  ///\r
+  UINT32        BootLoaderTolumSize;\r
+  UINT8         Reserved1[4];\r
+} FSPM_ARCH_CONFIG_PPI;\r
+\r
+extern EFI_GUID gFspmArchConfigPpiGuid;\r
+\r
+#endif // _FSPM_ARCH_CONFIG_PPI_H_\r

diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index 50496241dab14cf75b4017145949666e70ce615b..64a31b350539a15dadff87da96e17a66bef9bae8 100644 (file)
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -1,7 +1,7 @@
 ## @file\r
 # Provides driver and definitions to build fsp in EDKII bios.\r
 #\r
-# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
 # This program and the accompanying materials are licensed and made available under\r
 # the terms and conditions of the BSD License that accompanies this distribution.\r
 # The full text of the license may be found at\r
@@ -70,6 +70,9 @@
   gFspPerformanceDataGuid               = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }\r
   gFspEventEndOfFirmwareGuid            = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }\r
 \r
+[Ppis]\r
+  gFspmArchConfigPpiGuid                = { 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }\r
+\r
 [PcdsFixedAtBuild]\r
   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001\r
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase         |0xFEF00000|UINT32|0x10001001\r