REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
# ASSERT(). For ARM, AARCH64 and RISCV64, this I/O library only provides non I/O\r
# read and write.\r
#\r
# ASSERT(). For ARM, AARCH64 and RISCV64, this I/O library only provides non I/O\r
# read and write.\r
#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
[LibraryClasses]\r
DebugLib\r
BaseLib\r
[LibraryClasses]\r
DebugLib\r
BaseLib\r
## @file\r
# Instance of I/O Library using KVM/ARM safe assembler routines\r
#\r
## @file\r
# Instance of I/O Library using KVM/ARM safe assembler routines\r
#\r
-# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>\r
[LibraryClasses]\r
DebugLib\r
BaseLib\r
[LibraryClasses]\r
DebugLib\r
BaseLib\r
\r
This file includes package header files, dependent library classes.\r
\r
\r
This file includes package header files, dependent library classes.\r
\r
- Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#include <Library/IoLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
+#include <Library/RegisterFilterLib.h>\r
# I/O Library that uses compiler intrinsics to perform IN and OUT instructions\r
# for IA-32 and x64.\r
#\r
# I/O Library that uses compiler intrinsics to perform IN and OUT instructions\r
# for IA-32 and x64.\r
#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
#\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
#\r
[LibraryClasses]\r
DebugLib\r
BaseLib\r
[LibraryClasses]\r
DebugLib\r
BaseLib\r
/** @file\r
Common I/O Library routines.\r
\r
/** @file\r
Common I/O Library routines.\r
\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
- MemoryFence ();\r
- Value = *(volatile UINT8*)Address;\r
- MemoryFence ();\r
+ Flag = FilterBeforeMmIoRead (FilterWidth8, Address, &Value);\r
+ if (Flag) {\r
+ MemoryFence ();\r
+ Value = *(volatile UINT8*)Address;\r
+ MemoryFence ();\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth8, Address, &Value);\r
- MemoryFence ();\r
- *(volatile UINT8*)Address = Value;\r
- MemoryFence ();\r
+ BOOLEAN Flag;\r
+\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, &Value);\r
+ if (Flag) {\r
+ MemoryFence ();\r
+ *(volatile UINT8*)Address = Value;\r
+ MemoryFence ();\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth8, Address, &Value);\r
\r
ASSERT ((Address & 1) == 0);\r
\r
ASSERT ((Address & 1) == 0);\r
-\r
- MemoryFence ();\r
- Value = *(volatile UINT16*)Address;\r
- MemoryFence ();\r
+ Flag = FilterBeforeMmIoRead (FilterWidth16, Address, &Value);\r
+ if (Flag) {\r
+ MemoryFence ();\r
+ Value = *(volatile UINT16*)Address;\r
+ MemoryFence ();\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth16, Address, &Value);\r
IN UINT16 Value\r
)\r
{\r
IN UINT16 Value\r
)\r
{\r
ASSERT ((Address & 1) == 0);\r
\r
ASSERT ((Address & 1) == 0);\r
\r
- MemoryFence ();\r
- *(volatile UINT16*)Address = Value;\r
- MemoryFence ();\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth16, Address, &Value);\r
+ if (Flag) {\r
+ MemoryFence ();\r
+ *(volatile UINT16*)Address = Value;\r
+ MemoryFence ();\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth16, Address, &Value);\r
\r
ASSERT ((Address & 3) == 0);\r
\r
\r
ASSERT ((Address & 3) == 0);\r
\r
- MemoryFence ();\r
- Value = *(volatile UINT32*)Address;\r
- MemoryFence ();\r
+ Flag = FilterBeforeMmIoRead (FilterWidth32, Address, &Value);\r
+ if (Flag) {\r
+ MemoryFence ();\r
+ Value = *(volatile UINT32*)Address;\r
+ MemoryFence ();\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth32, Address, &Value);\r
IN UINT32 Value\r
)\r
{\r
IN UINT32 Value\r
)\r
{\r
ASSERT ((Address & 3) == 0);\r
\r
ASSERT ((Address & 3) == 0);\r
\r
- MemoryFence ();\r
- *(volatile UINT32*)Address = Value;\r
- MemoryFence ();\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth32, Address, &Value);\r
+ if (Flag) {\r
+ MemoryFence ();\r
+ *(volatile UINT32*)Address = Value;\r
+ MemoryFence ();\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth32, Address, &Value);\r
\r
ASSERT ((Address & 7) == 0);\r
\r
\r
ASSERT ((Address & 7) == 0);\r
\r
- MemoryFence ();\r
- Value = *(volatile UINT64*)Address;\r
- MemoryFence ();\r
+ Flag = FilterBeforeMmIoRead (FilterWidth64, Address, &Value);\r
+ if (Flag) {\r
+ MemoryFence ();\r
+ Value = *(volatile UINT64*)Address;\r
+ MemoryFence ();\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth64, Address, &Value);\r
IN UINT64 Value\r
)\r
{\r
IN UINT64 Value\r
)\r
{\r
ASSERT ((Address & 7) == 0);\r
\r
ASSERT ((Address & 7) == 0);\r
\r
- MemoryFence ();\r
- *(volatile UINT64*)Address = Value;\r
- MemoryFence ();\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth64, Address, &Value);\r
+ if (Flag) {\r
+ MemoryFence ();\r
+ *(volatile UINT64*)Address = Value;\r
+ MemoryFence ();\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth64, Address, &Value);\r
/** @file\r
I/O Library for ARM.\r
\r
/** @file\r
I/O Library for ARM.\r
\r
- Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>\r
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
- return MmioRead8Internal (Address);\r
+ UINT8 Value;\r
+ BOOLEAN Flag;\r
+\r
+ Flag = FilterBeforeMmIoRead (FilterWidth8, Address, &Value);\r
+ if (Flag) {\r
+ Value = MmioRead8Internal (Address);\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth8, Address, &Value);\r
+\r
+ return Value;\r
- MmioWrite8Internal (Address, Value);\r
+ BOOLEAN Flag;\r
+\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, &Value);\r
+ if (Flag) {\r
+ MmioWrite8Internal (Address, Value);\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth8, Address, &Value);\r
+\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
+ BOOLEAN Flag;\r
+ UINT16 Value;\r
+\r
ASSERT ((Address & 1) == 0);\r
\r
ASSERT ((Address & 1) == 0);\r
\r
- return MmioRead16Internal (Address);\r
+ Flag = FilterBeforeMmIoRead (FilterWidth16, Address, &Value);\r
+ if (Flag) {\r
+ Value = MmioRead16Internal (Address);\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth16, Address, &Value);\r
+\r
+ return Value;\r
IN UINT16 Value\r
)\r
{\r
IN UINT16 Value\r
)\r
{\r
ASSERT ((Address & 1) == 0);\r
\r
ASSERT ((Address & 1) == 0);\r
\r
- MmioWrite16Internal (Address, Value);\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth16, Address, &Value);\r
+ if (Flag) {\r
+ MmioWrite16Internal (Address, Value);\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth16, Address, &Value);\r
+\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
+ BOOLEAN Flag;\r
+ UINT32 Value;\r
+\r
ASSERT ((Address & 3) == 0);\r
\r
ASSERT ((Address & 3) == 0);\r
\r
- return MmioRead32Internal (Address);\r
+ Flag = FilterBeforeMmIoRead (FilterWidth32, Address, &Value);\r
+ if (Flag) {\r
+ Value = MmioRead32Internal (Address);\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth32, Address, &Value);\r
+\r
+ return Value;\r
IN UINT32 Value\r
)\r
{\r
IN UINT32 Value\r
)\r
{\r
ASSERT ((Address & 3) == 0);\r
\r
ASSERT ((Address & 3) == 0);\r
\r
- MmioWrite32Internal (Address, Value);\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth32, Address, &Value);\r
+ if (Flag) {\r
+ MmioWrite32Internal (Address, Value);\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth32, Address, &Value);\r
+\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
+ BOOLEAN Flag;\r
+ UINT64 Value;\r
+\r
ASSERT ((Address & 7) == 0);\r
\r
ASSERT ((Address & 7) == 0);\r
\r
- return MmioRead64Internal (Address);\r
+ Flag = FilterBeforeMmIoRead (FilterWidth64, Address, &Value);\r
+ if (Flag) {\r
+ Value = MmioRead64Internal (Address);\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth64, Address, &Value);\r
+\r
+ return Value;\r
IN UINT64 Value\r
)\r
{\r
IN UINT64 Value\r
)\r
{\r
ASSERT ((Address & 7) == 0);\r
\r
ASSERT ((Address & 7) == 0);\r
\r
- MmioWrite64Internal (Address, Value);\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth64, Address, &Value);\r
+ if (Flag) {\r
+ MmioWrite64Internal (Address, Value);\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth64, Address, &Value);\r
+\r
We don't advocate putting compiler specifics in libraries or drivers but there\r
is no other way to make this work.\r
\r
We don't advocate putting compiler specifics in libraries or drivers but there\r
is no other way to make this work.\r
\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
+ BOOLEAN Flag;\r
+\r
+ Flag = FilterBeforeIoRead (FilterWidth8, Port, &Data);\r
+ if (Flag) {\r
+ __asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));\r
+ }\r
+ FilterAfterIoRead (FilterWidth8, Port, &Data);\r
- __asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));\r
- __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
+ BOOLEAN Flag;\r
+\r
+ Flag = FilterBeforeIoWrite (FilterWidth8, Port, &Value);\r
+ if (Flag) {\r
+ __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
+ }\r
+ FilterAfterIoWrite (FilterWidth8, Port, &Value);\r
+\r
\r
ASSERT ((Port & 1) == 0);\r
\r
ASSERT ((Port & 1) == 0);\r
- __asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));\r
+\r
+ Flag = FilterBeforeIoRead (FilterWidth16, Port, &Data);\r
+ if (Flag) {\r
+ __asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));\r
+ }\r
+ FilterAfterIoRead (FilterWidth16, Port, &Data);\r
+\r
IN UINT16 Value\r
)\r
{\r
IN UINT16 Value\r
)\r
{\r
+\r
+ BOOLEAN Flag;\r
+\r
ASSERT ((Port & 1) == 0);\r
ASSERT ((Port & 1) == 0);\r
- __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
+\r
+ Flag = FilterBeforeIoWrite (FilterWidth16, Port, &Value);\r
+ if (Flag) {\r
+ __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
+ }\r
+ FilterAfterIoWrite (FilterWidth16, Port, &Value);\r
+\r
\r
ASSERT ((Port & 3) == 0);\r
\r
ASSERT ((Port & 3) == 0);\r
- __asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));\r
+\r
+ Flag = FilterBeforeIoRead (FilterWidth32, Port, &Data);\r
+ if (Flag) {\r
+ __asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));\r
+ }\r
+ FilterAfterIoRead (FilterWidth32, Port, &Data);\r
+\r
IN UINT32 Value\r
)\r
{\r
IN UINT32 Value\r
)\r
{\r
ASSERT ((Port & 3) == 0);\r
ASSERT ((Port & 3) == 0);\r
- __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
+\r
+ Flag = FilterBeforeIoWrite (FilterWidth32, Port, &Value);\r
+ if (Flag) {\r
+ __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
+ }\r
+ FilterAfterIoWrite (FilterWidth32, Port, &Value);\r
+\r
We don't advocate putting compiler specifics in libraries or drivers but there\r
is no other way to make this work.\r
\r
We don't advocate putting compiler specifics in libraries or drivers but there\r
is no other way to make this work.\r
\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
+ BOOLEAN Flag;\r
+\r
+ Flag = FilterBeforeIoRead (FilterWidth8, Port, &Value);\r
+ if (Flag) {\r
+ _ReadWriteBarrier ();\r
+ Value = (UINT8)_inp ((UINT16)Port);\r
+ _ReadWriteBarrier ();\r
+ }\r
+ FilterAfterIoRead (FilterWidth8, Port, &Value);\r
- _ReadWriteBarrier ();\r
- Value = (UINT8)_inp ((UINT16)Port);\r
- _ReadWriteBarrier ();\r
- _ReadWriteBarrier ();\r
- (UINT8)_outp ((UINT16)Port, Value);\r
- _ReadWriteBarrier ();\r
+ BOOLEAN Flag;\r
+\r
+ Flag = FilterBeforeIoWrite(FilterWidth8, Port, &Value);\r
+ if (Flag) {\r
+ _ReadWriteBarrier ();\r
+ (UINT8)_outp ((UINT16)Port, Value);\r
+ _ReadWriteBarrier ();\r
+ }\r
+ FilterAfterIoWrite (FilterWidth8, Port, &Value);\r
+\r
\r
ASSERT ((Port & 1) == 0);\r
\r
ASSERT ((Port & 1) == 0);\r
- _ReadWriteBarrier ();\r
- Value = _inpw ((UINT16)Port);\r
- _ReadWriteBarrier ();\r
+\r
+ Flag = FilterBeforeIoRead (FilterWidth16, Port, &Value);\r
+ if (Flag) {\r
+ _ReadWriteBarrier ();\r
+ Value = _inpw ((UINT16)Port);\r
+ _ReadWriteBarrier ();\r
+ }\r
+ FilterBeforeIoRead (FilterWidth16, Port, &Value);\r
+\r
IN UINT16 Value\r
)\r
{\r
IN UINT16 Value\r
)\r
{\r
ASSERT ((Port & 1) == 0);\r
ASSERT ((Port & 1) == 0);\r
- _ReadWriteBarrier ();\r
- _outpw ((UINT16)Port, Value);\r
- _ReadWriteBarrier ();\r
+\r
+ Flag = FilterBeforeIoWrite(FilterWidth16, Port, &Value);\r
+ if (Flag) {\r
+ _ReadWriteBarrier ();\r
+ _outpw ((UINT16)Port, Value);\r
+ _ReadWriteBarrier ();\r
+ }\r
+ FilterAfterIoWrite (FilterWidth16, Port, &Value);\r
+\r
\r
ASSERT ((Port & 3) == 0);\r
\r
ASSERT ((Port & 3) == 0);\r
- _ReadWriteBarrier ();\r
- Value = _inpd ((UINT16)Port);\r
- _ReadWriteBarrier ();\r
+\r
+ Flag = FilterBeforeIoRead(FilterWidth32, Port, &Value);\r
+ if (Flag) {\r
+ _ReadWriteBarrier ();\r
+ Value = _inpd ((UINT16)Port);\r
+ _ReadWriteBarrier ();\r
+ }\r
+ FilterAfterIoRead (FilterWidth32, Port, &Value);\r
+\r
IN UINT32 Value\r
)\r
{\r
IN UINT32 Value\r
)\r
{\r
ASSERT ((Port & 3) == 0);\r
ASSERT ((Port & 3) == 0);\r
- _ReadWriteBarrier ();\r
- _outpd ((UINT16)Port, Value);\r
- _ReadWriteBarrier ();\r
+\r
+ Flag = FilterBeforeIoWrite(FilterWidth32, Port, &Value);\r
+ if (Flag) {\r
+ _ReadWriteBarrier ();\r
+ _outpd ((UINT16)Port, Value);\r
+ _ReadWriteBarrier ();\r
+ }\r
+ FilterAfterIoWrite (FilterWidth32, Port, &Value);\r
+\r
I/O library for non I/O read and write access (memory map I/O read and\r
write only) architecture, such as ARM and RISC-V processor.\r
\r
I/O library for non I/O read and write access (memory map I/O read and\r
write only) architecture, such as ARM and RISC-V processor.\r
\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+ BOOLEAN Flag;\r
+\r
+ Flag = FilterBeforeMmIoRead (FilterWidth8, Address, &Value);\r
+ if (Flag) {\r
+ Value = *(volatile UINT8*)Address;\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth8, Address, &Value);\r
- Value = *(volatile UINT8*)Address;\r
- *(volatile UINT8*)Address = Value;\r
+ BOOLEAN Flag;\r
+\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, &Value);\r
+ if (Flag) {\r
+ *(volatile UINT8*)Address = Value;\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth8, Address, &Value);\r
+\r
\r
ASSERT ((Address & 1) == 0);\r
\r
ASSERT ((Address & 1) == 0);\r
- Value = *(volatile UINT16*)Address;\r
+\r
+ Flag = FilterBeforeMmIoRead (FilterWidth16, Address, &Value);\r
+ if (Flag) {\r
+ Value = *(volatile UINT16*)Address;\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth16, Address, &Value);\r
+\r
IN UINT16 Value\r
)\r
{\r
IN UINT16 Value\r
)\r
{\r
ASSERT ((Address & 1) == 0);\r
ASSERT ((Address & 1) == 0);\r
- *(volatile UINT16*)Address = Value;\r
+\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth16, Address, &Value);\r
+ if (Flag) {\r
+ *(volatile UINT16*)Address = Value;\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth16, Address, &Value);\r
+\r
\r
ASSERT ((Address & 3) == 0);\r
\r
ASSERT ((Address & 3) == 0);\r
- Value = *(volatile UINT32*)Address;\r
+\r
+ Flag = FilterBeforeMmIoRead (FilterWidth32, Address, &Value);\r
+ if (Flag) {\r
+ Value = *(volatile UINT32*)Address;\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth32, Address, &Value);\r
+\r
IN UINT32 Value\r
)\r
{\r
IN UINT32 Value\r
)\r
{\r
ASSERT ((Address & 3) == 0);\r
ASSERT ((Address & 3) == 0);\r
+\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth32, Address, &Value);\r
+ if (Flag) {\r
*(volatile UINT32*)Address = Value;\r
*(volatile UINT32*)Address = Value;\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth32, Address, &Value);\r
+\r
\r
ASSERT ((Address & 7) == 0);\r
\r
ASSERT ((Address & 7) == 0);\r
- Value = *(volatile UINT64*)Address;\r
+\r
+ Flag = FilterBeforeMmIoRead (FilterWidth64, Address, &Value);\r
+ if (Flag) {\r
+ Value = *(volatile UINT64*)Address;\r
+ }\r
+ FilterAfterMmIoRead (FilterWidth64, Address, &Value);\r
+\r
IN UINT64 Value\r
)\r
{\r
IN UINT64 Value\r
)\r
{\r
ASSERT ((Address & 7) == 0);\r
ASSERT ((Address & 7) == 0);\r
- *(volatile UINT64*)Address = Value;\r
+\r
+ Flag = FilterBeforeMmIoWrite (FilterWidth64, Address, &Value);\r
+ if (Flag) {\r
+ *(volatile UINT64*)Address = Value;\r
+ }\r
+ FilterAfterMmIoWrite (FilterWidth64, Address, &Value);\r
+\r