--- /dev/null
+/** @file\r
+ MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15.\r
+\r
+**/\r
+\r
+#ifndef __XEON_PHI_MSR_H__\r
+#define __XEON_PHI_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Thread. SMI Counter (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_SMI_COUNT 0x00000034\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] SMI Count (R/O).\r
+ ///\r
+ UINT32 SMICount:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_SMI_COUNT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. See http://biosbits.org.\r
+\r
+ @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
+ /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
+ /// MHz.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:12;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+ /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+ /// Turbo mode is disabled.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
+ /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
+ /// programmable.\r
+ ///\r
+ UINT32 TDPLimit:1;\r
+ UINT32 Reserved3:2;\r
+ UINT32 Reserved4:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
+ /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+ /// units of 100MHz.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved5:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Module. C-State Configuration Control (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code\r
+ /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No\r
+ /// Retention 011b: C6 Retention 111b: No limit.\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:16;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Module. Power Management IO Redirection in C-state (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] LVL_2 Base Address (R/W).\r
+ ///\r
+ UINT32 Lvl2Base:16;\r
+ ///\r
+ /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
+ /// maximum C-State code name to be included when IO read to MWAIT\r
+ /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4\r
+ /// is the max C-State to include 110b - C6 is the max C-State to include.\r
+ ///\r
+ UINT32 CStateRange:3;\r
+ UINT32 Reserved1:13;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+ handler to handle unsuccessful read of this MSR.\r
+\r
+ @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
+ /// MSR, the configuration of AES instruction set availability is as\r
+ /// follows: 11b: AES instructions are not available until next RESET.\r
+ /// otherwise, AES instructions are available. Note, AES instruction set\r
+ /// is not available if read is unsuccessful. If the configuration is not\r
+ /// 01b, AES instruction can be mis-configured if a privileged agent\r
+ /// unintentionally writes 11b.\r
+ ///\r
+ UINT32 AESConfiguration:2;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fast-Strings Enable.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W).\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Performance Monitoring Available (R).\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 11] Branch Trace Storage Unavailable (RO).\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Precise Event Based Sampling Unavailable (RO).\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 18] ENABLE MONITOR FSM (R/W).\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved6:3;\r
+ ///\r
+ /// [Bit 22] Limit CPUID Maxval (R/W).\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] xTPR Message Disable (R/W).\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 34] XD Bit Disable (R/W).\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved9:3;\r
+ ///\r
+ /// [Bit 38] Turbo Mode Disable (R/W).\r
+ ///\r
+ UINT32 TurboModeDisable:1;\r
+ UINT32 Reserved10:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (R).\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ ///\r
+ /// [Bits 29:24] Target Offset (R/W).\r
+ ///\r
+ UINT32 TargetOffset:6;\r
+ UINT32 Reserved2:2;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r
+\r
+\r
+/**\r
+ Shared. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).\r
+\r
+ @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved:1;\r
+ ///\r
+ /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active\r
+ /// processor cores which operates under the maximum ratio limit for group\r
+ /// 0.\r
+ ///\r
+ UINT32 MaxCoresGroup0:7;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo\r
+ /// ratio limit when the number of active cores are not more than the\r
+ /// group 0 maximum core count.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup0:8;\r
+ ///\r
+ /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1\r
+ /// Group 1, which includes the specified number of additional cores plus\r
+ /// the cores in group 0, operates under the group 1 turbo max ratio limit\r
+ /// = "group 0 Max ratio limit" - "group ratio delta for group 1".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup1:5;\r
+ ///\r
+ /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// to Group 0.\r
+ ///\r
+ UINT32 DeltaRatioGroup1:3;\r
+ ///\r
+ /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2\r
+ /// Group 2, which includes the specified number of additional cores plus\r
+ /// all the cores in group 1, operates under the group 2 turbo max ratio\r
+ /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup2:5;\r
+ ///\r
+ /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 1.\r
+ ///\r
+ UINT32 DeltaRatioGroup2:3;\r
+ ///\r
+ /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3\r
+ /// Group 3, which includes the specified number of additional cores plus\r
+ /// all the cores in group 2, operates under the group 3 turbo max ratio\r
+ /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup3:5;\r
+ ///\r
+ /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 2.\r
+ ///\r
+ UINT32 DeltaRatioGroup3:3;\r
+ ///\r
+ /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4\r
+ /// Group 4, which includes the specified number of additional cores plus\r
+ /// all the cores in group 3, operates under the group 4 turbo max ratio\r
+ /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup4:5;\r
+ ///\r
+ /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 3.\r
+ ///\r
+ UINT32 DeltaRatioGroup4:3;\r
+ ///\r
+ /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5\r
+ /// Group 5, which includes the specified number of additional cores plus\r
+ /// all the cores in group 4, operates under the group 5 turbo max ratio\r
+ /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup5:5;\r
+ ///\r
+ /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 4.\r
+ ///\r
+ UINT32 DeltaRatioGroup5:3;\r
+ ///\r
+ /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6\r
+ /// Group 6, which includes the specified number of additional cores plus\r
+ /// all the cores in group 5, operates under the group 6 turbo max ratio\r
+ /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup6:5;\r
+ ///\r
+ /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 5.\r
+ ///\r
+ UINT32 DeltaRatioGroup6:3;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record Filtering Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record Stack TOS (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Thread. Last Exception Record From Linear IP (R).\r
+\r
+ @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Thread. Last Exception Record To Linear IP (R).\r
+\r
+ @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ Thread. See Table 35-2.\r
+\r
+ @param ECX MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
+\r
+\r
+/**\r
+ Thread. See Table 35-2.\r
+\r
+ @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3\r
+ Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r
+\r
+\r
+/**\r
+ Package. Package C6 Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r
+\r
+\r
+/**\r
+ Package. Package C7 Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r
+\r
+\r
+/**\r
+ Module. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0\r
+ Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r
+\r
+\r
+/**\r
+ Module. Module C6 Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6\r
+ Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_XEON_PHI_MC3_CTL (0x0000040C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC3_CTL 0x0000040C\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
+\r
+ @param ECX MSR_XEON_PHI_MC3_STATUS (0x0000040D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC3_STATUS 0x0000040D\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".\r
+\r
+ @param ECX MSR_XEON_PHI_MC3_ADDR (0x0000040E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC3_ADDR 0x0000040E\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_XEON_PHI_MC4_CTL (0x00000410)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC4_CTL 0x00000410\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
+\r
+ @param ECX MSR_XEON_PHI_MC4_STATUS (0x00000411)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC4_STATUS 0x00000411\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register\r
+ is either not implemented or contains no address if the ADDRV flag in the\r
+ MSR_MC4_STATUS register is clear. When not implemented in the processor, all\r
+ reads and writes to this MSR will cause a general-protection exception.\r
+\r
+ @param ECX MSR_XEON_PHI_MC4_ADDR (0x00000412)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC4_ADDR 0x00000412\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_XEON_PHI_MC5_CTL (0x00000414)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC5_CTL 0x00000414\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
+\r
+ @param ECX MSR_XEON_PHI_MC5_STATUS (0x00000415)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC5_STATUS 0x00000415\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".\r
+\r
+ @param ECX MSR_XEON_PHI_MC5_ADDR (0x00000416)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MC5_ADDR 0x00000416\r
+\r
+\r
+/**\r
+ Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
+\r
+ @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
+\r
+\r
+/**\r
+ Core. Capability Reporting Register of VM-function Controls (R/O) See Table\r
+ 35-2.\r
+\r
+ @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Package. Energy Status Units Energy related information\r
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
+ /// micro-joules).\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
+ /// Interfaces.".\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2\r
+ Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r
+\r
+\r
+/**\r
+ Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r
+\r
+\r
+/**\r
+ Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
+ RAPL Domains.".\r
+\r
+ @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r
+\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Package. Base TDP Ratio (R/O) See Table 35-20.\r
+\r
+ @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-20.\r
+\r
+ @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-20.\r
+\r
+ @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Control (R/W) See Table 35-20.\r
+\r
+ @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Control (R/W) See Table 35-20.\r
+\r
+ @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
+ refers to processor core frequency).\r
+\r
+ @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0).\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0).\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0).\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 8] Electrical Design Point Status (R0).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 Reserved3:23;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+#endif\r
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