Remove hard code value and create new PCDs for OpROM reserved range in CSM module.

Signed-off-by: Li Elvin <elvin.li@intel.com>
Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13991 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c
index 0381098c8a8f64b8679c1f4aed8b68ebacdfe462..99a76c9f21acdd7b12f340621615c91122af8104 100644 (file)
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c
@@ -682,6 +682,7 @@ LegacyBiosInstall (
   LEGACY_BIOS_INSTANCE               *Private;\r
   EFI_TO_COMPATIBILITY16_INIT_TABLE  *EfiToLegacy16InitTable;\r
   EFI_PHYSICAL_ADDRESS               MemoryAddress;\r
   LEGACY_BIOS_INSTANCE               *Private;\r
   EFI_TO_COMPATIBILITY16_INIT_TABLE  *EfiToLegacy16InitTable;\r
   EFI_PHYSICAL_ADDRESS               MemoryAddress;\r

+  EFI_PHYSICAL_ADDRESS               EbdaReservedBaseAddress;\r

   VOID                               *MemoryPtr;\r
   EFI_PHYSICAL_ADDRESS               MemoryAddressUnder1MB;\r
   UINTN                              Index;\r
   VOID                               *MemoryPtr;\r
   EFI_PHYSICAL_ADDRESS               MemoryAddressUnder1MB;\r
   UINTN                              Index;\r


@@ -880,9 +881,21 @@ LegacyBiosInstall (
   //\r
   // Allocate all 32k chunks from 0x60000 ~ 0x88000 for Legacy OPROMs that\r
   // don't use PMM but look for zeroed memory. Note that various non-BBS\r
   //\r
   // Allocate all 32k chunks from 0x60000 ~ 0x88000 for Legacy OPROMs that\r
   // don't use PMM but look for zeroed memory. Note that various non-BBS\r

-  // SCSIs expect different areas to be free\r
+  // OpROMs expect different areas to be free\r

   //\r
   //\r

-  for (MemStart = 0x60000; MemStart < 0x88000; MemStart += 0x1000) {\r
+  EbdaReservedBaseAddress = MemoryAddress;\r
+  MemoryAddress = PcdGet32 (PcdOpromReservedMemoryBase);\r
+  MemorySize    = PcdGet32 (PcdOpromReservedMemorySize);\r
+  //\r
+  // Check if base address and size for reserved memory are 4KB aligned.\r
+  //\r
+  ASSERT ((MemoryAddress & 0xFFF) == 0);\r
+  ASSERT ((MemorySize & 0xFFF) == 0);\r
+  //\r
+  // Check if the reserved memory is below EBDA reserved range.\r
+  //\r
+  ASSERT ((MemoryAddress < EbdaReservedBaseAddress) && ((MemoryAddress + MemorySize - 1) < EbdaReservedBaseAddress));\r
+  for (MemStart = MemoryAddress; MemStart < MemoryAddress + MemorySize; MemStart += 0x1000) {\r

     Status = AllocateLegacyMemory (\r
                AllocateAddress,\r
                MemStart,\r
     Status = AllocateLegacyMemory (\r
                AllocateAddress,\r
                MemStart,\r

diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf
index ea8cb6bd084c7a0b896fb0dd5827d8497c86d95e..a5ad0dfd26e0d278cc4a364fd42ae97bbb724ce2 100644 (file)
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf
@@ -140,6 +140,8 @@
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEndOpromShadowAddress\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLowPmmMemorySize\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHighPmmMemorySize\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEndOpromShadowAddress\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLowPmmMemorySize\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHighPmmMemorySize\r

+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemoryBase\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemorySize\r

 \r
 [Depex]\r
   gEfiLegacyRegion2ProtocolGuid AND gEfiLegacyInterruptProtocolGuid AND gEfiLegacyBiosPlatformProtocolGuid AND gEfiLegacy8259ProtocolGuid AND gEfiGenericMemTestProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid\r
 \r
 [Depex]\r
   gEfiLegacyRegion2ProtocolGuid AND gEfiLegacyInterruptProtocolGuid AND gEfiLegacyBiosPlatformProtocolGuid AND gEfiLegacy8259ProtocolGuid AND gEfiGenericMemTestProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid\r

diff --git a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
index b4083bc5f468d2246278a7e0826eafaab516feb7..ce671603422b579f21e0c14d52b1dcf3182d50a3 100644 (file)
--- a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+++ b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
@@ -199,6 +199,18 @@
   ## The value should be a multiple of 4KB.\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x30000005\r
 \r
   ## The value should be a multiple of 4KB.\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x30000005\r
 \r

+  ## The PCD is used to specify memory base address for OPROM to find free memory.\r
+  # Some OPROMs do not use EBDA or PMM to allocate memory for its usage, \r
+  # instead they find the memory filled with zero from 0x20000.\r
+  # The range should be below the EBDA reserved range from \r
+  # (CONVENTIONAL_MEMORY_TOP - PcdEbdaReservedMemorySize) to CONVENTIONAL_MEMORY_TOP.\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemoryBase|0x60000|UINT32|0x3000000c\r
+  \r
+  ## The PCD is used to specify memory size with bytes for OPROM to find free memory.\r
+  ## The value should be a multiple of 4KB. And the range should be below the EBDA reserved range from \r
+  # (CONVENTIONAL_MEMORY_TOP - PcdEbdaReservedMemorySize) to CONVENTIONAL_MEMORY_TOP.\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemorySize|0x28000|UINT32|0x3000000d\r
+\r

   ## The PCD is used to specify memory size with page number for a pre-allocated reserved memory to be used\r
   #  by PEI in S3 phase. The default size 32K. When changing the value of this PCD, the platform\r
   #  developer should make sure the memory size is large enough to meet PEI requiremnt in S3 phase.\r
   ## The PCD is used to specify memory size with page number for a pre-allocated reserved memory to be used\r
   #  by PEI in S3 phase. The default size 32K. When changing the value of this PCD, the platform\r
   #  developer should make sure the memory size is large enough to meet PEI requiremnt in S3 phase.\r