ArmPkg/Mmu: Fix literal number left shift bug

There is a hidden bug for below code:

(1 << BaseAddressAlignment) & *BlockEntrySize

From disassembly code, we can see the literal number 1 will be treated
as INT32 by compiler by default, and we'll get 0xFFFFFFFF80000000 when
BaseAddressAlignment is equal to 31. So we will always get 31 when
alignment is larger than 31.

    if ((1 << BaseAddressAlignment) & *BlockEntrySize) {
5224: f9404be0  ldr x0, [sp,#144]
5228: 2a0003e1  mov w1, w0
522c: 52800020  mov w0, #0x1                    // #1
5230: 1ac12000  lsl w0, w0, w1
5234: 93407c01  sxtw  x1, w0

The bug can be replayed on QEMU AARCH64; by adding some debug print,
we can see lots of level 1 tables created (for block of 1GB) even
when the region is large enough to use 512GB block size.

Use LowBitSet64() in BaseLib instead to fix the bug.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18423 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index 5b6c4537b552b3dc775d937bbc46078c0bb84f37..dc50e0e0ec1bdea439b8310333afcdf1cebf5c7b 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -276,8 +276,8 @@ GetBlockEntryListFromAddress (
     return NULL;\r
   }\r
 \r
-  // Ensure the required size is aligned on 4KB boundary\r
-  if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0) {\r
+  // Ensure the required size is aligned on 4KB boundary and not 0\r
+  if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0 || *BlockEntrySize == 0) {\r
     ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r
     return NULL;\r
   }\r
@@ -294,18 +294,10 @@ GetBlockEntryListFromAddress (
   // If the start address is 0x0 then we use the size of the region to identify the alignment\r
   if (RegionStart == 0) {\r
     // Identify the highest possible alignment for the Region Size\r
-    for (BaseAddressAlignment = 0; BaseAddressAlignment < 64; BaseAddressAlignment++) {\r
-      if ((1 << BaseAddressAlignment) & *BlockEntrySize) {\r
-        break;\r
-      }\r
-    }\r
+    BaseAddressAlignment = LowBitSet64 (*BlockEntrySize);\r
   } else {\r
     // Identify the highest possible alignment for the Base Address\r
-    for (BaseAddressAlignment = 0; BaseAddressAlignment < 64; BaseAddressAlignment++) {\r
-      if ((1 << BaseAddressAlignment) & RegionStart) {\r
-        break;\r
-      }\r
-    }\r
+    BaseAddressAlignment = LowBitSet64 (RegionStart);\r
   }\r
 \r
   // Identify the Page Level the RegionStart must belongs to\r