summary |
shortlog |
log |
commit | commitdiff |
tree
raw |
patch |
inline | side by side (from parent 1:
d6a1c70)
- excute -> execute
- Retrive -> Retrieve
- possilbe -> possible
- CONTINOUS -> CONTINUOUS
- storgage -> storage
- allcated -> allocated
- triggerred -> triggered
- paramter -> parameter
- perodically -> periodically
- retore -> restore
v2:
- ruturn -> return
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Lin <glin@suse.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
MtrrValidBitsMask & 0xfffffffffffff000ULL\r
@param[out] VariableMtrr The array to shadow variable MTRRs content\r
\r
MtrrValidBitsMask & 0xfffffffffffff000ULL\r
@param[out] VariableMtrr The array to shadow variable MTRRs content\r
\r
- @return The ruturn value of this paramter indicates the number of\r
+ @return The return value of this parameter indicates the number of\r
MTRRs which has been used.\r
**/\r
UINT32\r
MTRRs which has been used.\r
**/\r
UINT32\r
//\r
if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) {\r
//\r
//\r
if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) {\r
//\r
- // Old IDT handler has been executed, then retore CPU exception content to\r
+ // Old IDT handler has been executed, then restore CPU exception content to\r
// run new exception handler.\r
//\r
ArchRestoreExceptionContext (ExceptionType, SystemContext);\r
// run new exception handler.\r
//\r
ArchRestoreExceptionContext (ExceptionType, SystemContext);\r
/**\r
Checks APs' status periodically.\r
\r
/**\r
Checks APs' status periodically.\r
\r
- This function is triggerred by timer perodically to check the\r
+ This function is triggered by timer periodically to check the\r
state of APs for StartupAllAPs() and StartupThisAP() executed\r
in non-blocking mode.\r
\r
state of APs for StartupAllAPs() and StartupThisAP() executed\r
in non-blocking mode.\r
\r
@param[in] MtrrValidAddressMask The valid address mask for MTRR\r
@param[out] VariableMtrr The array to shadow variable MTRRs content\r
\r
@param[in] MtrrValidAddressMask The valid address mask for MTRR\r
@param[out] VariableMtrr The array to shadow variable MTRRs content\r
\r
- @return The return value of this paramter indicates the\r
+ @return The return value of this parameter indicates the\r
number of MTRRs which has been used.\r
\r
**/\r
number of MTRRs which has been used.\r
\r
**/\r
/** @file\r
This module produces the EFI_PEI_S3_RESUME2_PPI.\r
This module works with StandAloneBootScriptExecutor to S3 resume to OS.\r
/** @file\r
This module produces the EFI_PEI_S3_RESUME2_PPI.\r
This module works with StandAloneBootScriptExecutor to S3 resume to OS.\r
- This module will excute the boot script saved during last boot and after that,\r
+ This module will execute the boot script saved during last boot and after that,\r
control is passed to OS waking up handler.\r
\r
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
control is passed to OS waking up handler.\r
\r
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
- // Retrive time stamp count as early as possilbe\r
+ // Retrieve time stamp count as early as possible\r
//\r
Ticker = GetPerformanceCounter ();\r
\r
//\r
Ticker = GetPerformanceCounter ();\r
\r
// NOTE: We have to ASSUME the page table generation format, because we do not know whole page table information.\r
// The whole page table is too large to be saved in SMRAM.\r
//\r
// NOTE: We have to ASSUME the page table generation format, because we do not know whole page table information.\r
// The whole page table is too large to be saved in SMRAM.\r
//\r
- // The assumption is : whole page table is allocated in CONTINOUS memory and CR3 points to TOP page.\r
+ // The assumption is : whole page table is allocated in CONTINUOUS memory and CR3 points to TOP page.\r
//\r
DEBUG ((EFI_D_ERROR, "S3NvsPageTableAddress - %x (%x)\n", (UINTN)S3NvsPageTableAddress, (UINTN)Build4GPageTableOnly));\r
\r
//\r
//\r
DEBUG ((EFI_D_ERROR, "S3NvsPageTableAddress - %x (%x)\n", (UINTN)S3NvsPageTableAddress, (UINTN)Build4GPageTableOnly));\r
\r
//\r
- // By architecture only one PageMapLevel4 exists - so lets allocate storgage for it.\r
+ // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
//\r
PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;\r
S3NvsPageTableAddress += SIZE_4KB;\r
//\r
PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;\r
S3NvsPageTableAddress += SIZE_4KB;\r
//\r
IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
//\r
//\r
IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
//\r
- // Make sure the newly allcated IDT align with 16-bytes\r
+ // Make sure the newly allocated IDT align with 16-bytes\r
// \r
IdtBuffer = AllocatePages (EFI_SIZE_TO_PAGES((IdtDescriptor->Limit + 1) + 16));\r
if (IdtBuffer == NULL) {\r
// \r
IdtBuffer = AllocatePages (EFI_SIZE_TO_PAGES((IdtDescriptor->Limit + 1) + 16));\r
if (IdtBuffer == NULL) {\r