OvmfPkg/PciHostBridgeLib: Scan for root bridges when running over Xen

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Gary Lin <glin@suse.com>

diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridge.h b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridge.h
new file mode 100644 (file)
index 0000000..c23d40c
--- /dev/null
+++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridge.h
@@ -0,0 +1,75 @@
+/** @file\r
+  Header file of OVMF instance of PciHostBridgeLib.\r
+\r
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials are licensed and made available\r
+  under the terms and conditions of the BSD License which accompanies this\r
+  distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+PCI_ROOT_BRIDGE *\r
+ScanForRootBridges (\r
+  UINTN      *NumberOfRootBridges\r
+);\r
+\r
+/**\r
+  Initialize a PCI_ROOT_BRIDGE structure.\r
+\r
+  @param[in]  Supports         Supported attributes.\r
+\r
+  @param[in]  Attributes       Initial attributes.\r
+\r
+  @param[in]  AllocAttributes  Allocation attributes.\r
+\r
+  @param[in]  RootBusNumber    The bus number to store in RootBus.\r
+\r
+  @param[in]  MaxSubBusNumber  The inclusive maximum bus number that can be\r
+                               assigned to any subordinate bus found behind any\r
+                               PCI bridge hanging off this root bus.\r
+\r
+                               The caller is repsonsible for ensuring that\r
+                               RootBusNumber <= MaxSubBusNumber. If\r
+                               RootBusNumber equals MaxSubBusNumber, then the\r
+                               root bus has no room for subordinate buses.\r
+\r
+  @param[in]  Io               IO aperture.\r
+\r
+  @param[in]  Mem              MMIO aperture.\r
+\r
+  @param[in]  MemAbove4G       MMIO aperture above 4G.\r
+\r
+  @param[in]  PMem             Prefetchable MMIO aperture.\r
+\r
+  @param[in]  PMemAbove4G      Prefetchable MMIO aperture above 4G.\r
+\r
+  @param[out] RootBus          The PCI_ROOT_BRIDGE structure (allocated by the\r
+                               caller) that should be filled in by this\r
+                               function.\r
+\r
+  @retval EFI_SUCCESS           Initialization successful. A device path\r
+                                consisting of an ACPI device path node, with\r
+                                UID = RootBusNumber, has been allocated and\r
+                                linked into RootBus.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Memory allocation failed.\r
+**/\r
+EFI_STATUS\r
+InitRootBridge (\r
+  IN  UINT64                   Supports,\r
+  IN  UINT64                   Attributes,\r
+  IN  UINT64                   AllocAttributes,\r
+  IN  UINT8                    RootBusNumber,\r
+  IN  UINT8                    MaxSubBusNumber,\r
+  IN  PCI_ROOT_BRIDGE_APERTURE *Io,\r
+  IN  PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+  IN  PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+  IN  PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+  IN  PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,\r
+  OUT PCI_ROOT_BRIDGE          *RootBus\r
+  );\r

diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
index aeb0bdf84dcb7a9b7bb75b22f64322ac8b87eaf7..6ba0ca68314d807d35835099fa92d21ae045e0e4 100644 (file)
--- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -28,6 +28,7 @@
 #include <Library/PciHostBridgeLib.h>\r
 #include <Library/PciLib.h>\r
 #include <Library/QemuFwCfgLib.h>\r
+#include "PciHostBridge.h"\r
 \r
 \r
 #pragma pack(1)\r
@@ -113,7 +114,6 @@ STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };
 \r
   @retval EFI_OUT_OF_RESOURCES  Memory allocation failed.\r
 **/\r
-STATIC\r
 EFI_STATUS\r
 InitRootBridge (\r
   IN  UINT64                   Supports,\r
@@ -217,6 +217,10 @@ PciHostBridgeGetRootBridges (
   PCI_ROOT_BRIDGE_APERTURE Mem;\r
   PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r
 \r
+  if (PcdGetBool (PcdPciDisableBusEnumeration)) {\r
+    return ScanForRootBridges (Count);\r
+  }\r
+\r
   Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
     EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
     EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r

diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 7a964c74c6cce45f54d864a9ac68733a39803611..046ffbde8e9249a7a1d38a7589c26ebbe19f7e73 100644 (file)
--- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -32,6 +32,8 @@
 \r
 [Sources]\r
   PciHostBridgeLib.c\r
+  XenSupport.c\r
+  PciHostBridge.h\r
 \r
 [Packages]\r
   MdeModulePkg/MdeModulePkg.dec\r
@@ -54,3 +56,4 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base\r
   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration\r

diff --git a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c
new file mode 100644 (file)
index 0000000..2189663
--- /dev/null
+++ b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c
@@ -0,0 +1,456 @@
+/** @file\r
+  Scan the entire PCI bus for root bridges to support OVMF above Xen.\r
+\r
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials are licensed and made available\r
+  under the terms and conditions of the BSD License which accompanies this\r
+  distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#include <PiDxe.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <IndustryStandard/Q35MchIch9.h>\r
+\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PciHostBridgeLib.h>\r
+#include <Library/PciLib.h>\r
+#include "PciHostBridge.h"\r
+\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeBarExisted (\r
+  IN  UINT64                         Address,\r
+  OUT UINT32                         *OriginalValue,\r
+  OUT UINT32                         *Value\r
+  )\r
+{\r
+  //\r
+  // Preserve the original value\r
+  //\r
+  *OriginalValue = PciRead32 (Address);\r
+\r
+  //\r
+  // Disable timer interrupt while the BAR is probed\r
+  //\r
+  DisableInterrupts ();\r
+\r
+  PciWrite32 (Address, 0xFFFFFFFF);\r
+  *Value = PciRead32 (Address);\r
+  PciWrite32 (Address, *OriginalValue);\r
+\r
+  //\r
+  // Enable interrupt\r
+  //\r
+  EnableInterrupts ();\r
+}\r
+\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeParseBars (\r
+  IN UINT16                         Command,\r
+  IN UINTN                          Bus,\r
+  IN UINTN                          Device,\r
+  IN UINTN                          Function,\r
+  IN UINTN                          BarOffsetBase,\r
+  IN UINTN                          BarOffsetEnd,\r
+  IN PCI_ROOT_BRIDGE_APERTURE       *Io,\r
+  IN PCI_ROOT_BRIDGE_APERTURE       *Mem,\r
+  IN PCI_ROOT_BRIDGE_APERTURE       *MemAbove4G,\r
+  IN PCI_ROOT_BRIDGE_APERTURE       *PMem,\r
+  IN PCI_ROOT_BRIDGE_APERTURE       *PMemAbove4G\r
+\r
+)\r
+{\r
+  UINT32                            OriginalValue;\r
+  UINT32                            Value;\r
+  UINT32                            OriginalUpperValue;\r
+  UINT32                            UpperValue;\r
+  UINT64                            Mask;\r
+  UINTN                             Offset;\r
+  UINT64                            Base;\r
+  UINT64                            Length;\r
+  UINT64                            Limit;\r
+  PCI_ROOT_BRIDGE_APERTURE          *MemAperture;\r
+\r
+  for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r
+    PcatPciRootBridgeBarExisted (\r
+      PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+      &OriginalValue, &Value\r
+    );\r
+    if (Value == 0) {\r
+      continue;\r
+    }\r
+    if ((Value & BIT0) == BIT0) {\r
+      //\r
+      // IO Bar\r
+      //\r
+      if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
+        Mask = 0xfffffffc;\r
+        Base = OriginalValue & Mask;\r
+        Length = ((~(Value & Mask)) & Mask) + 0x04;\r
+        if (!(Value & 0xFFFF0000)) {\r
+          Length &= 0x0000FFFF;\r
+        }\r
+        Limit = Base + Length - 1;\r
+\r
+        if (Base < Limit) {\r
+          if (Io->Base > Base) {\r
+            Io->Base = Base;\r
+          }\r
+          if (Io->Limit < Limit) {\r
+            Io->Limit = Limit;\r
+          }\r
+        }\r
+      }\r
+    } else {\r
+      //\r
+      // Mem Bar\r
+      //\r
+      if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
+\r
+        Mask = 0xfffffff0;\r
+        Base = OriginalValue & Mask;\r
+        Length = Value & Mask;\r
+\r
+        if ((Value & (BIT1 | BIT2)) == 0) {\r
+          //\r
+          // 32bit\r
+          //\r
+          Length = ((~Length) + 1) & 0xffffffff;\r
+\r
+          if ((Value & BIT3) == BIT3) {\r
+            MemAperture = PMem;\r
+          } else {\r
+            MemAperture = Mem;\r
+          }\r
+        } else {\r
+          //\r
+          // 64bit\r
+          //\r
+          Offset += 4;\r
+          PcatPciRootBridgeBarExisted (\r
+            PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+            &OriginalUpperValue,\r
+            &UpperValue\r
+          );\r
+\r
+          Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
+          Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
+          Length = (~Length) + 1;\r
+\r
+          if ((Value & BIT3) == BIT3) {\r
+            MemAperture = PMemAbove4G;\r
+          } else {\r
+            MemAperture = MemAbove4G;\r
+          }\r
+        }\r
+\r
+        Limit = Base + Length - 1;\r
+        if (Base < Limit) {\r
+          if (MemAperture->Base > Base) {\r
+            MemAperture->Base = Base;\r
+          }\r
+          if (MemAperture->Limit < Limit) {\r
+            MemAperture->Limit = Limit;\r
+          }\r
+        }\r
+      }\r
+    }\r
+  }\r
+}\r
+\r
+PCI_ROOT_BRIDGE *\r
+ScanForRootBridges (\r
+  UINTN      *NumberOfRootBridges\r
+  )\r
+{\r
+  UINTN      PrimaryBus;\r
+  UINTN      SubBus;\r
+  UINT8      Device;\r
+  UINT8      Function;\r
+  UINTN      NumberOfDevices;\r
+  UINT64     Address;\r
+  PCI_TYPE01 Pci;\r
+  UINT64     Attributes;\r
+  UINT64     Base;\r
+  UINT64     Limit;\r
+  UINT64     Value;\r
+  PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;\r
+  PCI_ROOT_BRIDGE *RootBridges;\r
+  UINTN      BarOffsetEnd;\r
+\r
+\r
+  *NumberOfRootBridges = 0;\r
+  RootBridges = NULL;\r
+\r
+  //\r
+  // After scanning all the PCI devices on the PCI root bridge's primary bus,\r
+  // update the Primary Bus Number for the next PCI root bridge to be this PCI\r
+  // root bridge's subordinate bus number + 1.\r
+  //\r
+  for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
+    SubBus = PrimaryBus;\r
+    Attributes = 0;\r
+    Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r
+    Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;\r
+    //\r
+    // Scan all the PCI devices on the primary bus of the PCI root bridge\r
+    //\r
+    for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
+\r
+      for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
+\r
+        //\r
+        // Compute the PCI configuration address of the PCI device to probe\r
+        //\r
+        Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);\r
+\r
+        //\r
+        // Read the Vendor ID from the PCI Configuration Header\r
+        //\r
+        if (PciRead16 (Address) == MAX_UINT16) {\r
+          if (Function == 0) {\r
+            //\r
+            // If the PCI Configuration Read fails, or a PCI device does not\r
+            // exist, then skip this entire PCI device\r
+            //\r
+            break;\r
+          } else {\r
+            //\r
+            // If PCI function != 0, VendorId == 0xFFFF, we continue to search\r
+            // PCI function.\r
+            //\r
+            continue;\r
+          }\r
+        }\r
+\r
+        //\r
+        // Read the entire PCI Configuration Header\r
+        //\r
+        PciReadBuffer (Address, sizeof (Pci), &Pci);\r
+\r
+        //\r
+        // Increment the number of PCI device found on the primary bus of the\r
+        // PCI root bridge\r
+        //\r
+        NumberOfDevices++;\r
+\r
+        //\r
+        // Look for devices with the VGA Palette Snoop enabled in the COMMAND\r
+        // register of the PCI Config Header\r
+        //\r
+        if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
+          Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+          Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+        }\r
+\r
+        BarOffsetEnd = 0;\r
+\r
+        //\r
+        // PCI-PCI Bridge\r
+        //\r
+        if (IS_PCI_BRIDGE (&Pci)) {\r
+          //\r
+          // Get the Bus range that the PPB is decoding\r
+          //\r
+          if (Pci.Bridge.SubordinateBus > SubBus) {\r
+            //\r
+            // If the suborinate bus number of the PCI-PCI bridge is greater\r
+            // than the PCI root bridge's current subordinate bus number,\r
+            // then update the PCI root bridge's subordinate bus number\r
+            //\r
+            SubBus = Pci.Bridge.SubordinateBus;\r
+          }\r
+\r
+          //\r
+          // Get the I/O range that the PPB is decoding\r
+          //\r
+          Value = Pci.Bridge.IoBase & 0x0f;\r
+          Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r
+          Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
+          if (Value == BIT0) {\r
+            Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r
+            Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r
+          }\r
+          if (Base < Limit) {\r
+            if (Io.Base > Base) {\r
+              Io.Base = Base;\r
+            }\r
+            if (Io.Limit < Limit) {\r
+              Io.Limit = Limit;\r
+            }\r
+          }\r
+\r
+          //\r
+          // Get the Memory range that the PPB is decoding\r
+          //\r
+          Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
+          Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
+          if (Base < Limit) {\r
+            if (Mem.Base > Base) {\r
+              Mem.Base = Base;\r
+            }\r
+            if (Mem.Limit < Limit) {\r
+              Mem.Limit = Limit;\r
+            }\r
+          }\r
+\r
+          //\r
+          // Get the Prefetchable Memory range that the PPB is decoding\r
+          //\r
+          Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
+          Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
+          Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
+                   << 16) | 0xfffff;\r
+          MemAperture = &PMem;\r
+          if (Value == BIT0) {\r
+            Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
+            Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
+            MemAperture = &PMemAbove4G;\r
+          }\r
+          if (Base < Limit) {\r
+            if (MemAperture->Base > Base) {\r
+              MemAperture->Base = Base;\r
+            }\r
+            if (MemAperture->Limit < Limit) {\r
+              MemAperture->Limit = Limit;\r
+            }\r
+          }\r
+\r
+          //\r
+          // Look at the PPB Configuration for legacy decoding attributes\r
+          //\r
+          if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r
+              == EFI_PCI_BRIDGE_CONTROL_ISA) {\r
+            Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+            Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+            Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+          }\r
+          if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r
+              == EFI_PCI_BRIDGE_CONTROL_VGA) {\r
+            Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+            Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+            Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+            if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r
+                != 0) {\r
+              Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+              Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+            }\r
+          }\r
+\r
+          BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);\r
+        } else {\r
+          //\r
+          // Parse the BARs of the PCI device to get what I/O Ranges, Memory\r
+          // Ranges, and Prefetchable Memory Ranges the device is decoding\r
+          //\r
+          if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r
+            BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);\r
+          }\r
+        }\r
+\r
+        PcatPciRootBridgeParseBars (\r
+          Pci.Hdr.Command,\r
+          PrimaryBus,\r
+          Device,\r
+          Function,\r
+          OFFSET_OF (PCI_TYPE00, Device.Bar),\r
+          BarOffsetEnd,\r
+          &Io,\r
+          &Mem, &MemAbove4G,\r
+          &PMem, &PMemAbove4G\r
+        );\r
+\r
+        //\r
+        // See if the PCI device is an IDE controller\r
+        //\r
+        if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r
+                       PCI_CLASS_MASS_STORAGE_IDE)) {\r
+          if (Pci.Hdr.ClassCode[0] & 0x80) {\r
+            Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+            Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+          }\r
+          if (Pci.Hdr.ClassCode[0] & 0x01) {\r
+            Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+          }\r
+          if (Pci.Hdr.ClassCode[0] & 0x04) {\r
+            Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+          }\r
+        }\r
+\r
+        //\r
+        // See if the PCI device is a legacy VGA controller or\r
+        // a standard VGA controller\r
+        //\r
+        if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r
+            IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r
+            ) {\r
+          Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+          Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+          Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+          Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+          Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+        }\r
+\r
+        //\r
+        // See if the PCI Device is a PCI - ISA or PCI - EISA\r
+        // or ISA_POSITIVIE_DECODE Bridge device\r
+        //\r
+        if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
+          if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r
+              Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r
+              Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r
+            Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+            Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+            Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+          }\r
+        }\r
+\r
+        //\r
+        // If this device is not a multi function device, then skip the rest\r
+        // of this PCI device\r
+        //\r
+        if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
+          break;\r
+        }\r
+      }\r
+    }\r
+\r
+    //\r
+    // If at least one PCI device was found on the primary bus of this PCI\r
+    // root bridge, then the PCI root bridge exists.\r
+    //\r
+    if (NumberOfDevices > 0) {\r
+      RootBridges = ReallocatePool (\r
+        (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
+        (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
+        RootBridges\r
+      );\r
+      ASSERT (RootBridges != NULL);\r
+      InitRootBridge (\r
+        Attributes, Attributes, 0,\r
+        (UINT8) PrimaryBus, (UINT8) SubBus,\r
+        &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,\r
+        &RootBridges[*NumberOfRootBridges]\r
+      );\r
+      RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r
+      //\r
+      // Increment the index for the next PCI Root Bridge\r
+      //\r
+      (*NumberOfRootBridges)++;\r
+    }\r
+  }\r
+\r
+  return RootBridges;\r
+}\r