+++ /dev/null
-#\r
-# Copyright (c) 2013-2015, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-[Defines]\r
- DEC_SPECIFICATION = 0x00010005\r
- PACKAGE_NAME = ArmJunoPkg\r
- PACKAGE_GUID = a1147a20-3144-4f8d-8295-b48311c8e4a4\r
- PACKAGE_VERSION = 0.1\r
-\r
-################################################################################\r
-#\r
-# Include Section - list of Include Paths that are provided by this package.\r
-# Comments are used for Keywords and Module Types.\r
-#\r
-# Supported Module Types:\r
-# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
-#\r
-################################################################################\r
-[Includes.common]\r
- Include # Root include for the package\r
-\r
-[Guids.common]\r
- gArmJunoTokenSpaceGuid = { 0xa1147a20, 0x3144, 0x4f8d, { 0x82, 0x95, 0xb4, 0x83, 0x11, 0xc8, 0xe4, 0xa4 } }\r
-\r
-[PcdsFeatureFlag.common]\r
- gArmJunoTokenSpaceGuid.PcdPciMaxPayloadFixup|FALSE|BOOLEAN|0x00000013\r
-\r
-[PcdsFixedAtBuild.common]\r
- gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress|0x7FF20000|UINT64|0x0000000B\r
- gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress|0x7FF30000|UINT64|0x0000000C\r
- gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress|0x40000000|UINT64|0x00000011\r
- gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize|0x10000000|UINT64|0x00000012\r
-\r
- gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress|0x7FFB0000|UINT32|0x00000004\r
- gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress|0x7FFC0000|UINT32|0x00000005\r
-\r
- # Juno Device Trees are loaded from NOR Flash\r
- gArmJunoTokenSpaceGuid.PcdJunoFdtDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/board.dtb"|VOID*|0x00000008\r
+++ /dev/null
-/** @file\r
-\r
- This file contains support for ACPI Tables that are generated at boot time.\r
-\r
- Copyright (c) 2015, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "ArmPlatform.h"\r
-#include "ArmJunoDxeInternal.h"\r
-\r
-#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>\r
-\r
-/*\r
- * Memory Mapped Configuration Space Access Table (MCFG)\r
- */\r
-typedef struct {\r
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;\r
- EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Entry;\r
-} MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ACCESS_TABLE;\r
-\r
-MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ACCESS_TABLE mAcpiMcfgTable = {\r
- {\r
- ARM_ACPI_HEADER (\r
- EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,\r
- MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ACCESS_TABLE,\r
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION\r
- ),\r
- 0, // Reserved\r
- }, {\r
- FixedPcdGet32 (PcdPciConfigurationSpaceBaseAddress),\r
- 0, // PciSegmentGroupNumber\r
- FixedPcdGet32 (PcdPciBusMin),\r
- FixedPcdGet32 (PcdPciBusMax),\r
- 0 // Reserved;\r
- }\r
-};\r
-\r
-/**\r
- * Callback called when ACPI Protocol is installed\r
- */\r
-VOID\r
-AcpiPciNotificationEvent (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;\r
- UINTN AcpiTableKey;\r
-\r
- //\r
- // Ensure the ACPI protocol is installed\r
- //\r
- Status = gBS->LocateProtocol (\r
- &gEfiAcpiTableProtocolGuid,\r
- NULL,\r
- (VOID**)&AcpiTableProtocol\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return;\r
- }\r
-\r
- //\r
- // Install MCFG Table\r
- //\r
- AcpiTableKey = 0;\r
- Status = AcpiTableProtocol->InstallAcpiTable (AcpiTableProtocol, &mAcpiMcfgTable, sizeof (mAcpiMcfgTable), &AcpiTableKey);\r
- ASSERT_EFI_ERROR (Status);\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013-2015, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include "ArmJunoDxeInternal.h"\r
-#include <ArmPlatform.h>\r
-\r
-#include <IndustryStandard/Pci.h>\r
-#include <Protocol/DevicePathFromText.h>\r
-#include <Protocol/PciIo.h>\r
-#include <Protocol/PciRootBridgeIo.h>\r
-\r
-#include <Guid/EventGroup.h>\r
-#include <Guid/GlobalVariable.h>\r
-\r
-#include <Library/ArmShellCmdLib.h>\r
-#include <Library/AcpiLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/DevicePathLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/NonDiscoverableDeviceRegistrationLib.h>\r
-#include <Library/UefiRuntimeServicesTableLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/PrintLib.h>\r
-\r
-\r
-// This GUID must match the FILE_GUID in ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf\r
-STATIC CONST EFI_GUID mJunoAcpiTableFile = { 0xa1dd808e, 0x1e95, 0x4399, { 0xab, 0xc0, 0x65, 0x3c, 0x82, 0xe8, 0x53, 0x0c } };\r
-\r
-typedef struct {\r
- ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
- PCI_DEVICE_PATH PciDevicePath;\r
- EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
-} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
-\r
-STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mPciRootComplexDevicePath = {\r
- {\r
- { ACPI_DEVICE_PATH,\r
- ACPI_DP,\r
- { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),\r
- (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) }\r
- },\r
- EISA_PNP_ID (0x0A03),\r
- 0\r
- },\r
- {\r
- { HARDWARE_DEVICE_PATH,\r
- HW_PCI_DP,\r
- { (UINT8) (sizeof (PCI_DEVICE_PATH)),\r
- (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) }\r
- },\r
- 0,\r
- 0\r
- },\r
- {\r
- END_DEVICE_PATH_TYPE,\r
- END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
- { END_DEVICE_PATH_LENGTH, 0 }\r
- }\r
-};\r
-\r
-EFI_EVENT mAcpiRegistration = NULL;\r
-\r
-/**\r
- This function reads PCI ID of the controller.\r
-\r
- @param[in] PciIo PCI IO protocol handle\r
- @param[in] PciId Looking for specified PCI ID Vendor/Device\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-ReadMarvellYoukonPciId (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 PciId\r
- )\r
-{\r
- UINT32 DevicePciId;\r
- EFI_STATUS Status;\r
-\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- PCI_VENDOR_ID_OFFSET,\r
- 1,\r
- &DevicePciId);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- if (DevicePciId != PciId) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- This function searches for Marvell Yukon NIC on the Juno\r
- platform and returns PCI IO protocol handle for the controller.\r
-\r
- @param[out] PciIo PCI IO protocol handle\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-GetMarvellYukonPciIoProtocol (\r
- OUT EFI_PCI_IO_PROTOCOL **PciIo\r
- )\r
-{\r
- UINTN HandleCount;\r
- EFI_HANDLE *HandleBuffer;\r
- UINTN HIndex;\r
- EFI_STATUS Status;\r
-\r
- Status = gBS->LocateHandleBuffer (\r
- ByProtocol,\r
- &gEfiPciIoProtocolGuid,\r
- NULL,\r
- &HandleCount,\r
- &HandleBuffer);\r
- if (EFI_ERROR (Status)) {\r
- return (Status);\r
- }\r
-\r
- for (HIndex = 0; HIndex < HandleCount; ++HIndex) {\r
- // If PciIo opened with EFI_OPEN_PROTOCOL_GET_PROTOCOL, the CloseProtocol() is not required\r
- Status = gBS->OpenProtocol (\r
- HandleBuffer[HIndex],\r
- &gEfiPciIoProtocolGuid,\r
- (VOID **) PciIo,\r
- NULL,\r
- NULL,\r
- EFI_OPEN_PROTOCOL_GET_PROTOCOL);\r
- if (EFI_ERROR (Status)) {\r
- continue;\r
- }\r
-\r
- Status = ReadMarvellYoukonPciId (*PciIo, JUNO_MARVELL_YUKON_ID);\r
- if (EFI_ERROR (Status)) {\r
- continue;\r
- } else {\r
- break;\r
- }\r
- }\r
-\r
- gBS->FreePool (HandleBuffer);\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- This function restore the original controller attributes\r
-\r
- @param[in] PciIo PCI IO protocol handle\r
- @param[in] PciAttr PCI controller attributes.\r
- @param[in] AcpiResDescriptor ACPI 2.0 resource descriptors for the BAR\r
-**/\r
-STATIC\r
-VOID\r
-RestorePciDev (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT64 PciAttr\r
- )\r
-{\r
- PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationSet,\r
- PciAttr,\r
- NULL\r
- );\r
-}\r
-\r
-/**\r
- This function returns PCI MMIO base address for a controller\r
-\r
- @param[in] PciIo PCI IO protocol handle\r
- @param[out] PciRegBase PCI base MMIO address\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-BarIsDeviceMemory (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- OUT UINT32 *PciRegBase\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiResDescriptor;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiCurrentDescriptor;\r
-\r
- // Marvell Yukon's Bar0 provides base memory address for control registers\r
- Status = PciIo->GetBarAttributes (PciIo, PCI_BAR_IDX0, NULL, (VOID**)&AcpiResDescriptor);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- AcpiCurrentDescriptor = AcpiResDescriptor;\r
-\r
- // Search for a memory type descriptor\r
- while (AcpiCurrentDescriptor->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
-\r
- // Check if Bar is memory type one and fetch a base address\r
- if (AcpiCurrentDescriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR &&\r
- AcpiCurrentDescriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM &&\r
- !(AcpiCurrentDescriptor->SpecificFlag & ACPI_SPECFLAG_PREFETCHABLE)) {\r
- *PciRegBase = AcpiCurrentDescriptor->AddrRangeMin;\r
- break;\r
- } else {\r
- Status = EFI_UNSUPPORTED;\r
- }\r
-\r
- AcpiCurrentDescriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (AcpiCurrentDescriptor + 1);\r
- }\r
-\r
- gBS->FreePool (AcpiResDescriptor);\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- This function provides PCI MMIO base address, old PCI controller attributes.\r
-\r
- @param[in] PciIo PCI IO protocol handle\r
- @param[out] PciRegBase PCI base MMIO address\r
- @param[out] OldPciAttr Old PCI controller attributes.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-InitPciDev (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- OUT UINT32 *PciRegBase,\r
- OUT UINT64 *OldPciAttr\r
- )\r
-{\r
- UINT64 AttrSupports;\r
- EFI_STATUS Status;\r
-\r
- // Get controller's current attributes\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationGet,\r
- 0,\r
- OldPciAttr);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- // Fetch supported attributes\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationSupported,\r
- 0,\r
- &AttrSupports);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- // Enable EFI_PCI_IO_ATTRIBUTE_IO, EFI_PCI_IO_ATTRIBUTE_MEMORY and\r
- // EFI_PCI_IO_ATTRIBUTE_BUS_MASTER bits in the PCI Config Header\r
- AttrSupports &= EFI_PCI_DEVICE_ENABLE;\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationEnable,\r
- AttrSupports,\r
- NULL);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- Status = BarIsDeviceMemory (PciIo, PciRegBase);\r
- if (EFI_ERROR (Status)) {\r
- RestorePciDev (PciIo, *OldPciAttr);\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- This function reads MAC address from IOFPGA and writes it to Marvell Yukon NIC\r
-\r
- @param[in] PciRegBase PCI base MMIO address\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-WriteMacAddress (\r
- IN UINT32 PciRegBase\r
- )\r
-{\r
- UINT32 MacHigh;\r
- UINT32 MacLow;\r
-\r
- // Read MAC address from IOFPGA\r
- MacHigh= MmioRead32 (ARM_JUNO_SYS_PCIGBE_H);\r
- MacLow = MmioRead32 (ARM_JUNO_SYS_PCIGBE_L);\r
-\r
- // Set software reset control register to protect from deactivation\r
- // the config write state\r
- MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_CLR);\r
-\r
- // Convert to Marvell MAC Address register format\r
- MacHigh = SwapBytes32 ((MacHigh & 0xFFFF) << 16 |\r
- (MacLow & 0xFFFF0000) >> 16);\r
- MacLow = SwapBytes32 (MacLow) >> 16;\r
-\r
- // Set MAC Address\r
- MmioWrite8 (PciRegBase + R_TST_CTRL_1, TST_CFG_WRITE_ENABLE);\r
- MmioWrite32 (PciRegBase + R_MAC, MacHigh);\r
- MmioWrite32 (PciRegBase + R_MAC_MAINT, MacHigh);\r
- MmioWrite32 (PciRegBase + R_MAC + R_MAC_LOW, MacLow);\r
- MmioWrite32 (PciRegBase + R_MAC_MAINT + R_MAC_LOW, MacLow);\r
- MmioWrite8 (PciRegBase + R_TST_CTRL_1, TST_CFG_WRITE_DISABLE);\r
-\r
- // Initiate device reset\r
- MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_SET);\r
- MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_CLR);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- The function reads MAC address from Juno IOFPGA registers and writes it\r
- into Marvell Yukon NIC.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-ArmJunoSetNicMacAddress ()\r
-{\r
- UINT64 OldPciAttr;\r
- EFI_PCI_IO_PROTOCOL* PciIo;\r
- UINT32 PciRegBase;\r
- EFI_STATUS Status;\r
-\r
- Status = GetMarvellYukonPciIoProtocol (&PciIo);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- PciRegBase = 0;\r
- Status = InitPciDev (PciIo, &PciRegBase, &OldPciAttr);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- Status = WriteMacAddress (PciRegBase);\r
-\r
- RestorePciDev (PciIo, OldPciAttr);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Notification function of the event defined as belonging to the\r
- EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in\r
- the entry point of the driver.\r
-\r
- This function is called when an event belonging to the\r
- EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an\r
- event is signalled once at the end of the dispatching of all\r
- drivers (end of the so called DXE phase).\r
-\r
- @param[in] Event Event declared in the entry point of the driver whose\r
- notification function is being invoked.\r
- @param[in] Context NULL\r
-**/\r
-STATIC\r
-VOID\r
-OnEndOfDxe (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
- )\r
-{\r
- EFI_DEVICE_PATH_PROTOCOL* PciRootComplexDevicePath;\r
- EFI_HANDLE Handle;\r
- EFI_STATUS Status;\r
-\r
- //\r
- // PCI Root Complex initialization\r
- // At the end of the DXE phase, we should get all the driver dispatched.\r
- // Force the PCI Root Complex to be initialized. It allows the OS to skip\r
- // this step.\r
- //\r
- PciRootComplexDevicePath = (EFI_DEVICE_PATH_PROTOCOL*) &mPciRootComplexDevicePath;\r
- Status = gBS->LocateDevicePath (&gEfiPciRootBridgeIoProtocolGuid,\r
- &PciRootComplexDevicePath,\r
- &Handle);\r
-\r
- Status = gBS->ConnectController (Handle, NULL, PciRootComplexDevicePath, FALSE);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- Status = ArmJunoSetNicMacAddress ();\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "ArmJunoDxe: Failed to set Marvell Yukon NIC MAC address\n"));\r
- }\r
-}\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-ArmJunoEntryPoint (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS HypBase;\r
- CHAR16 *TextDevicePath;\r
- UINTN TextDevicePathSize;\r
- VOID *Buffer;\r
- UINT32 JunoRevision;\r
- EFI_EVENT EndOfDxeEvent;\r
-\r
- //\r
- // Register the OHCI and EHCI controllers as non-coherent\r
- // non-discoverable devices.\r
- //\r
- Status = RegisterNonDiscoverableMmioDevice (\r
- NonDiscoverableDeviceTypeOhci,\r
- NonDiscoverableDeviceDmaTypeNonCoherent,\r
- NULL,\r
- NULL,\r
- 1,\r
- FixedPcdGet32 (PcdSynopsysUsbOhciBaseAddress),\r
- SIZE_64KB\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- Status = RegisterNonDiscoverableMmioDevice (\r
- NonDiscoverableDeviceTypeEhci,\r
- NonDiscoverableDeviceDmaTypeNonCoherent,\r
- NULL,\r
- NULL,\r
- 1,\r
- FixedPcdGet32 (PcdSynopsysUsbEhciBaseAddress),\r
- SIZE_64KB\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // If a hypervisor has been declared then we need to make sure its region is protected at runtime\r
- //\r
- // Note: This code is only a workaround for our dummy hypervisor (ArmPkg/Extra/AArch64ToAArch32Shim/)\r
- // that does not set up (yet) the stage 2 translation table to hide its own memory to EL1.\r
- //\r
- if (FixedPcdGet32 (PcdHypFvSize) != 0) {\r
- // Ensure the hypervisor region is strictly contained into a EFI_PAGE_SIZE-aligned region.\r
- // The memory must be a multiple of EFI_PAGE_SIZE to ensure we do not reserve more memory than the hypervisor itself.\r
- // A UEFI Runtime region size granularity cannot be smaller than EFI_PAGE_SIZE. If the hypervisor size is not rounded\r
- // to this size then there is a risk some non-runtime memory could be visible to the OS view.\r
- if (((FixedPcdGet32 (PcdHypFvSize) & EFI_PAGE_MASK) == 0) && ((FixedPcdGet32 (PcdHypFvBaseAddress) & EFI_PAGE_MASK) == 0)) {\r
- // The memory needs to be declared because the DXE core marked it as reserved and removed it from the memory space\r
- // as it contains the Firmware.\r
- Status = gDS->AddMemorySpace (\r
- EfiGcdMemoryTypeSystemMemory,\r
- FixedPcdGet32 (PcdHypFvBaseAddress), FixedPcdGet32 (PcdHypFvSize),\r
- EFI_MEMORY_WB | EFI_MEMORY_RUNTIME\r
- );\r
- if (!EFI_ERROR (Status)) {\r
- // We allocate the memory to ensure it is marked as runtime memory\r
- HypBase = FixedPcdGet32 (PcdHypFvBaseAddress);\r
- Status = gBS->AllocatePages (AllocateAddress, EfiRuntimeServicesCode,\r
- EFI_SIZE_TO_PAGES (FixedPcdGet32 (PcdHypFvSize)), &HypBase);\r
- }\r
- } else {\r
- // The hypervisor must be contained into a EFI_PAGE_SIZE-aligned region and its size must also be aligned\r
- // on a EFI_PAGE_SIZE boundary (ie: 4KB).\r
- Status = EFI_UNSUPPORTED;\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- }\r
-\r
- // Install dynamic Shell command to run baremetal binaries.\r
- Status = ShellDynCmdRunAxfInstall (ImageHandle);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "ArmJunoDxe: Failed to install ShellDynCmdRunAxf\n"));\r
- }\r
-\r
- GetJunoRevision(JunoRevision);\r
-\r
- //\r
- // Try to install the ACPI Tables\r
- //\r
- Status = LocateAndInstallAcpiFromFv (&mJunoAcpiTableFile);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Setup R1/R2 options if not already done.\r
- //\r
- if (JunoRevision != JUNO_REVISION_R0) {\r
- // Enable PCI enumeration\r
- PcdSetBool (PcdPciDisableBusEnumeration, FALSE);\r
-\r
- //\r
- // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group.\r
- // The "OnEndOfDxe()" function is declared as the call back function.\r
- // It will be called at the end of the DXE phase when an event of the\r
- // same group is signalled to inform about the end of the DXE phase.\r
- // Install the INSTALL_FDT_PROTOCOL protocol.\r
- //\r
- Status = gBS->CreateEventEx (\r
- EVT_NOTIFY_SIGNAL,\r
- TPL_CALLBACK,\r
- OnEndOfDxe,\r
- NULL,\r
- &gEfiEndOfDxeEventGroupGuid,\r
- &EndOfDxeEvent\r
- );\r
-\r
- // Declare the related ACPI Tables\r
- EfiCreateProtocolNotifyEvent (\r
- &gEfiAcpiTableProtocolGuid,\r
- TPL_CALLBACK,\r
- AcpiPciNotificationEvent,\r
- NULL,\r
- &mAcpiRegistration\r
- );\r
- }\r
-\r
- //\r
- // Set up the device path to the FDT.\r
- //\r
- TextDevicePath = (CHAR16*)FixedPcdGetPtr (PcdJunoFdtDevicePath);\r
- if (TextDevicePath != NULL) {\r
- TextDevicePathSize = StrSize (TextDevicePath);\r
- Buffer = PcdSetPtr (PcdFdtDevicePaths, &TextDevicePathSize, TextDevicePath);\r
- Status = (Buffer != NULL) ? EFI_SUCCESS : EFI_BUFFER_TOO_SMALL;\r
- } else {\r
- Status = EFI_NOT_FOUND;\r
- }\r
-\r
- if (EFI_ERROR (Status)) {\r
- DEBUG (\r
- (EFI_D_ERROR,\r
- "ArmJunoDxe: Setting of FDT device path in PcdFdtDevicePaths failed - %r\n", Status)\r
- );\r
- return Status;\r
- }\r
-\r
- return Status;\r
-}\r
+++ /dev/null
-#\r
-# Copyright (c) 2013-2015, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmJunoDxe\r
- FILE_GUID = 1484ebe8-2681-45f1-a2e5-12ecad893b62\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- ENTRY_POINT = ArmJunoEntryPoint\r
-\r
-[Sources.common]\r
- AcpiTables.c\r
- ArmJunoDxe.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec\r
- ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
-\r
-[LibraryClasses]\r
- AcpiLib\r
- ArmLib\r
- ArmShellCmdRunAxfLib\r
- BaseMemoryLib\r
- DebugLib\r
- DxeServicesTableLib\r
- IoLib\r
- NonDiscoverableDeviceRegistrationLib\r
- PcdLib\r
- PrintLib\r
- SerialPortLib\r
- UefiBootServicesTableLib\r
- UefiRuntimeServicesTableLib\r
- UefiLib\r
- UefiDriverEntryPoint\r
-\r
-[Guids]\r
- gEfiEndOfDxeEventGroupGuid\r
- gEfiFileInfoGuid\r
-\r
-[Protocols]\r
- gEfiBlockIoProtocolGuid\r
- gEfiDevicePathFromTextProtocolGuid\r
- gEfiPciIoProtocolGuid\r
- gEfiPciRootBridgeIoProtocolGuid\r
- gEfiSimpleFileSystemProtocolGuid\r
- gEfiAcpiTableProtocolGuid\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
-\r
- gArmTokenSpaceGuid.PcdHypFvBaseAddress\r
- gArmTokenSpaceGuid.PcdHypFvSize\r
-\r
- gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress\r
- gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress\r
-\r
- gArmJunoTokenSpaceGuid.PcdJunoFdtDevicePath\r
-\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument\r
-\r
- # PCI Root complex specific PCDs\r
- gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress\r
- gArmTokenSpaceGuid.PcdPciBusMin\r
- gArmTokenSpaceGuid.PcdPciBusMax\r
-\r
-[Pcd]\r
- gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration\r
-\r
-[Depex]\r
- # We depend on these protocols to create the default boot entries\r
- gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013-2015, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __ARM_JUNO_DXE_INTERNAL_H__\r
-#define __ARM_JUNO_DXE_INTERNAL_H__\r
-\r
-#include <Uefi.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/AcpiLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/DxeServicesTableLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/UefiLib.h>\r
-\r
-#include <Protocol/AcpiTable.h>\r
-\r
-#include <IndustryStandard/Acpi.h>\r
-\r
-#define ACPI_SPECFLAG_PREFETCHABLE 0x06\r
-#define JUNO_MARVELL_YUKON_ID 0x438011AB /* Juno Marvell PCI Dev ID */\r
-#define TST_CFG_WRITE_ENABLE 0x02 /* Enable Config Write */\r
-#define TST_CFG_WRITE_DISABLE 0x00 /* Disable Config Write */\r
-#define CS_RESET_CLR 0x02 /* SW Reset Clear */\r
-#define CS_RESET_SET 0x00 /* SW Reset Set */\r
-#define R_CONTROL_STATUS 0x0004 /* Control/Status Register */\r
-#define R_MAC 0x0100 /* MAC Address */\r
-#define R_MAC_MAINT 0x0110 /* MAC Address Maintenance */\r
-#define R_MAC_LOW 0x04 /* MAC Address Low Register Offset */\r
-#define R_TST_CTRL_1 0x0158 /* Test Control Register 1 */\r
-\r
-\r
-/**\r
- * Callback called when ACPI Protocol is installed\r
- */\r
-VOID\r
-AcpiPciNotificationEvent (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
- );\r
-\r
-#endif // __ARM_JUNO_DXE_INTERNAL_H__\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013-2017, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __ARM_JUNO_H__\r
-#define __ARM_JUNO_H__\r
-\r
-#include <VExpressMotherBoard.h>\r
-\r
-/***********************************************************************************\r
-// Platform Memory Map\r
-************************************************************************************/\r
-\r
-// Motherboard Peripheral and On-chip peripheral\r
-#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000\r
-#define ARM_VE_BOARD_SYS_ID 0x0000\r
-#define ARM_VE_BOARD_SYS_PCIE_GBE_L 0x0074\r
-#define ARM_VE_BOARD_SYS_PCIE_GBE_H 0x0078\r
-\r
-#define ARM_VE_BOARD_SYS_ID_REV(word) ((word >> 28) & 0xff)\r
-\r
-// NOR Flash 0\r
-#define ARM_VE_SMB_NOR0_BASE 0x08000000\r
-#define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r
-\r
-// Off-Chip peripherals (USB, Ethernet, VRAM)\r
-#define ARM_VE_SMB_PERIPH_BASE 0x18000000\r
-#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_2MB)\r
-\r
-// On-Chip non-secure ROM\r
-#define ARM_JUNO_NON_SECURE_ROM_BASE 0x1F000000\r
-#define ARM_JUNO_NON_SECURE_ROM_SZ SIZE_16MB\r
-\r
-// On-Chip Peripherals\r
-#define ARM_JUNO_PERIPHERALS_BASE 0x20000000\r
-#define ARM_JUNO_PERIPHERALS_SZ 0x0E000000\r
-\r
-// PCIe MSI address window\r
-#define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c0000\r
-#define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB\r
-\r
-// PCIe MSI to SPI mapping range\r
-#define ARM_JUNO_GIV2M_MSI_SPI_BASE 224\r
-#define ARM_JUNO_GIV2M_MSI_SPI_COUNT 127 //TRM says last SPI is 351, 351-224=127\r
-\r
-// On-Chip non-secure SRAM\r
-#define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000\r
-#define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB\r
-\r
-// SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)\r
-#define ARM_JUNO_SOC_PERIPHERALS_BASE 0x7FF50000\r
-#define ARM_JUNO_SOC_PERIPHERALS_SZ (SIZE_64KB * 9)\r
-\r
-// 6GB of DRAM from the 64bit address space\r
-#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE 0x0880000000\r
-#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ (SIZE_2GB + SIZE_4GB)\r
-\r
-//\r
-// ACPI table information used to initialize tables.\r
-//\r
-#define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long\r
-#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long\r
-#define EFI_ACPI_ARM_OEM_REVISION 0x20140727\r
-#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')\r
-#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099\r
-\r
-// A macro to initialise the common header part of EFI ACPI tables as defined by\r
-// EFI_ACPI_DESCRIPTION_HEADER structure.\r
-#define ARM_ACPI_HEADER(Signature, Type, Revision) { \\r
- Signature, /* UINT32 Signature */ \\r
- sizeof (Type), /* UINT32 Length */ \\r
- Revision, /* UINT8 Revision */ \\r
- 0, /* UINT8 Checksum */ \\r
- { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \\r
- EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \\r
- EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \\r
- EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \\r
- EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \\r
- }\r
-\r
-//\r
-// Hardware platform identifiers\r
-//\r
-#define JUNO_REVISION_PROTOTYPE 0\r
-#define JUNO_REVISION_R0 1\r
-#define JUNO_REVISION_R1 2\r
-#define JUNO_REVISION_R2 3\r
-#define JUNO_REVISION_UKNOWN 0xFF\r
-\r
-//\r
-// We detect whether we are running on a Juno r0, r1 or r2\r
-// board at runtime by checking the value of board SYS_ID\r
-//\r
-#define GetJunoRevision(JunoRevision) \\r
-{ \\r
- UINT32 SysId; \\r
- SysId = MmioRead32 (ARM_VE_BOARD_PERIPH_BASE+ARM_VE_BOARD_SYS_ID); \\r
- JunoRevision = ARM_VE_BOARD_SYS_ID_REV( SysId ); \\r
-}\r
-\r
-\r
-// Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest\r
-//#define ARM_JUNO_ACPI_5_0\r
-\r
-//\r
-// Address of the system registers that contain the MAC address\r
-// assigned to the PCI Gigabyte Ethernet device.\r
-//\r
-\r
-#define ARM_JUNO_SYS_PCIGBE_L (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_L)\r
-#define ARM_JUNO_SYS_PCIGBE_H (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_H)\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Library/ArmLib.h>\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-// With this function: CorePos = (ClusterId * 2) + CoreId\r
-ASM_FUNC(ArmPlatformGetCorePosition)\r
- and x1, x0, #ARM_CORE_MASK\r
- and x0, x0, #ARM_CLUSTER_MASK\r
- add x0, x1, x0, LSR #7\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
- ldr w0, PrimaryCoreMpid\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ASM_FUNC(ArmPlatformIsPrimaryCore)\r
- MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))\r
- and x0, x0, x1\r
-\r
- ldr w1, PrimaryCoreMpid\r
-\r
- cmp w0, w1\r
- cset x0, eq\r
- ret\r
-\r
-ASM_FUNC(ArmPlatformPeiBootAction)\r
- // The trusted firmware passes the primary CPU MPID through x0 register.\r
- // Save it in a variable.\r
- adr x1, PrimaryCoreMpid\r
- str w0, [x1]\r
- ret\r
-\r
-PrimaryCoreMpid: .word 0x0\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/ArmLib.h>\r
-\r
-//\r
-// Return the core position from the value of its MpId register\r
-//\r
-// This function returns the core position from the position 0 in the processor.\r
-// This function might be called from assembler before any stack is set.\r
-//\r
-// @return Return the core position\r
-//\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-// With this function: CorePos = (ClusterId * 2) + CoreId\r
-ASM_FUNC(ArmPlatformGetCorePosition)\r
- and r1, r0, #ARM_CORE_MASK\r
- and r0, r0, #ARM_CLUSTER_MASK\r
- add r0, r1, r0, LSR #7\r
- bx lr\r
-\r
-//\r
-// Return the MpId of the primary core\r
-//\r
-// This function returns the MpId of the primary core.\r
-// This function might be called from assembler before any stack is set.\r
-//\r
-// @return Return the MpId of the primary core\r
-//\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
- LDRL (r0, PrimaryCoreMpid)\r
- bx lr\r
-\r
-//\r
-// Return a non-zero value if the callee is the primary core\r
-//\r
-// This function returns a non-zero value if the callee is the primary core.\r
-// The primary core is the core responsible to initialize the hardware and run UEFI.\r
-// This function might be called from assembler before any stack is set.\r
-//\r
-// @return Return a non-zero value if the callee is the primary core.\r
-//\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ASM_FUNC(ArmPlatformIsPrimaryCore)\r
- MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))\r
- and r0, r0, r1\r
-\r
- LDRL (r1, PrimaryCoreMpid)\r
-\r
- cmp r0, r1\r
- moveq r0, #1\r
- movne r0, #0\r
- bx lr\r
-\r
-//\r
-// First platform specific function to be called in the PEI phase\r
-//\r
-// This function is actually the first function called by the PrePi\r
-// or PrePeiCore modules. It allows to retrieve arguments passed to\r
-// the UEFI firmware through the CPU registers.\r
-//\r
-ASM_FUNC(ArmPlatformPeiBootAction)\r
- // The trusted firmware passes the primary CPU MPID through r0 register.\r
- // Save it in a variable.\r
- adr r1, PrimaryCoreMpid\r
- str r0, [r1]\r
- bx lr\r
-\r
-PrimaryCoreMpid: .word 0x0\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013-2016, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Drivers/PL011Uart.h>\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Ppi/ArmMpCoreInfo.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-ARM_CORE_INFO mJunoInfoTable[] = {\r
- {\r
- // Cluster 0, Core 0\r
- 0x0, 0x0,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 0, Core 1\r
- 0x0, 0x1,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 1, Core 0\r
- 0x1, 0x0,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 1, Core 1\r
- 0x1, 0x1,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 1, Core 2\r
- 0x1, 0x2,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 1, Core 3\r
- 0x1, 0x3,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- }\r
-};\r
-\r
-/**\r
- Return the current Boot Mode\r
-\r
- This function returns the boot reason on the platform\r
-\r
- @return Return the current Boot Mode of the platform\r
-\r
-**/\r
-EFI_BOOT_MODE\r
-ArmPlatformGetBootMode (\r
- VOID\r
- )\r
-{\r
- return BOOT_WITH_FULL_CONFIGURATION;\r
-}\r
-\r
-/**\r
- Initialize controllers that must setup in the normal world\r
-\r
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim\r
- in the PEI phase.\r
-\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformInitialize (\r
- IN UINTN MpId\r
- )\r
-{\r
- RETURN_STATUS Status;\r
- UINT64 BaudRate;\r
- UINT32 ReceiveFifoDepth;\r
- EFI_PARITY_TYPE Parity;\r
- UINT8 DataBits;\r
- EFI_STOP_BITS_TYPE StopBits;\r
-\r
- Status = RETURN_SUCCESS;\r
-\r
- //\r
- // Initialize the Serial Debug UART\r
- //\r
- if (FixedPcdGet64 (PcdSerialDbgRegisterBase)) {\r
- ReceiveFifoDepth = 0; // Use the default value for FIFO depth\r
- Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);\r
- DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);\r
- StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);\r
-\r
- BaudRate = (UINTN)FixedPcdGet64 (PcdSerialDbgUartBaudRate);\r
- Status = PL011UartInitializePort (\r
- (UINTN)FixedPcdGet64 (PcdSerialDbgRegisterBase),\r
- FixedPcdGet32 (PcdSerialDbgUartClkInHz),\r
- &BaudRate,\r
- &ReceiveFifoDepth,\r
- &Parity,\r
- &DataBits,\r
- &StopBits\r
- );\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- Initialize the system (or sometimes called permanent) memory\r
-\r
- This memory is generally represented by the DRAM.\r
-\r
-**/\r
-VOID\r
-ArmPlatformInitializeSystemMemory (\r
- VOID\r
- )\r
-{\r
-}\r
-\r
-EFI_STATUS\r
-PrePeiCoreGetMpCoreInfo (\r
- OUT UINTN *CoreCount,\r
- OUT ARM_CORE_INFO **ArmCoreTable\r
- )\r
-{\r
- // Only support one cluster\r
- *CoreCount = sizeof(mJunoInfoTable) / sizeof(ARM_CORE_INFO);\r
- *ArmCoreTable = mJunoInfoTable;\r
- return EFI_SUCCESS;\r
-}\r
-\r
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
-\r
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r
- {\r
- EFI_PEI_PPI_DESCRIPTOR_PPI,\r
- &gArmMpCoreInfoPpiGuid,\r
- &mMpCoreInfoPpi\r
- }\r
-};\r
-\r
-VOID\r
-ArmPlatformGetPlatformPpiList (\r
- OUT UINTN *PpiListSize,\r
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
- )\r
-{\r
- *PpiListSize = sizeof(gPlatformPpiTable);\r
- *PpiList = gPlatformPpiTable;\r
-}\r
+++ /dev/null
-#\r
-# Copyright (c) 2013-2016, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmJunoLib\r
- FILE_GUID = 87c525cd-e1a2-469e-994c-c28cd0c7bd0d\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec\r
-\r
-[LibraryClasses]\r
- IoLib\r
- ArmLib\r
- HobLib\r
- MemoryAllocationLib\r
- SerialPortLib\r
-\r
-[Sources.common]\r
- ArmJuno.c\r
- ArmJunoMem.c\r
-\r
-[Sources.AARCH64]\r
- AArch64/ArmJunoHelper.S\r
-\r
-[Sources.ARM]\r
- Arm/ArmJunoHelper.S | GCC\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
-\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
-\r
- gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress\r
- gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress\r
- gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize\r
-\r
-\r
- #\r
- # PL011 Serial Debug UART\r
- #\r
- gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase\r
- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate\r
- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz\r
-\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
-\r
-[Pcd]\r
- gArmTokenSpaceGuid.PcdPciMmio32Base\r
- gArmTokenSpaceGuid.PcdPciMmio32Size\r
- gArmTokenSpaceGuid.PcdPciMmio64Base\r
- gArmTokenSpaceGuid.PcdPciMmio64Size\r
-\r
-[Ppis]\r
- gArmMpCoreInfoPpiGuid\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013-2015, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/HobLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-// The total number of descriptors, including the final "end-of-table" descriptor.\r
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16\r
-\r
-// DDR attributes\r
-#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
-\r
-/**\r
- Return the Virtual Memory Map of your platform\r
-\r
- This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
-\r
- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
- Virtual Memory mapping. This array must be ended by a zero-filled\r
- entry\r
-\r
-**/\r
-VOID\r
-ArmPlatformGetVirtualMemoryMap (\r
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
- )\r
-{\r
- ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
- UINTN Index = 0;\r
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;\r
-\r
- ASSERT (VirtualMemoryMap != NULL);\r
-\r
- //\r
- // Declared the additional 6GB of memory\r
- //\r
- ResourceAttributes =\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED;\r
-\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- ResourceAttributes,\r
- ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE,\r
- ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ);\r
-\r
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
- if (VirtualMemoryTable == NULL) {\r
- return;\r
- }\r
-\r
- if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
- CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
- } else {\r
- CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
- }\r
-\r
- // SMB CS0 - NOR0 Flash\r
- VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].Length = SIZE_256KB * 255;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
- // Environment Variables region\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
- VirtualMemoryTable[Index].Length = SIZE_64KB * 4;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // SMB CS2 & CS3 - Off-chip (motherboard) peripherals\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // Juno OnChip non-secure ROM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_ROM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_ROM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_ROM_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // Juno OnChip peripherals\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_PERIPHERALS_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_PERIPHERALS_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_JUNO_PERIPHERALS_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // Juno OnChip non-secure SRAM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_SRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_SRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_SRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // PCI Root Complex\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieControlBaseAddress);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieControlBaseAddress);\r
- VirtualMemoryTable[Index].Length = SIZE_128KB;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- //\r
- // PCI Configuration Space\r
- //\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);\r
- VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciConfigurationSpaceSize);\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- //\r
- // PCI Memory Space\r
- //\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base);\r
- VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size);\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- //\r
- // 64-bit PCI Memory Space\r
- //\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base);\r
- VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size);\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // Juno SOC peripherals\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_SOC_PERIPHERALS_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_SOC_PERIPHERALS_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_JUNO_SOC_PERIPHERALS_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // DDR - 2GB\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // DDR - 6GB\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // End of Table\r
- VirtualMemoryTable[++Index].PhysicalBase = 0;\r
- VirtualMemoryTable[Index].VirtualBase = 0;\r
- VirtualMemoryTable[Index].Length = 0;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
-\r
- ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
-\r
- *VirtualMemoryMap = VirtualMemoryTable;\r
-}\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- **/\r
-\r
-#include <PiDxe.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/NorFlashPlatformLib.h>\r
-#include <ArmPlatform.h>\r
-\r
-NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {\r
- {\r
- ARM_VE_SMB_NOR0_BASE,\r
- ARM_VE_SMB_NOR0_BASE,\r
- SIZE_256KB * 255,\r
- SIZE_256KB,\r
- {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59} }\r
- },\r
- {\r
- ARM_VE_SMB_NOR0_BASE,\r
- ARM_VE_SMB_NOR0_BASE + SIZE_256KB * 255,\r
- SIZE_64KB * 4,\r
- SIZE_64KB,\r
- {0x02118005, 0x9DA7, 0x443A, { 0x92, 0xD5, 0x78, 0x1F, 0x02, 0x2A, 0xED, 0xBB } }\r
- },\r
-};\r
-\r
-EFI_STATUS\r
-NorFlashPlatformInitialization (\r
- VOID\r
- )\r
-{\r
- // Everything seems ok so far, so now we need to disable the platform-specific\r
- // flash write protection for Versatile Express\r
- if ((MmioRead32 (ARM_VE_SYS_FLASH) & 0x1) == 0) {\r
- // Writing to NOR FLASH is disabled, so enable it\r
- MmioWrite32 (ARM_VE_SYS_FLASH, 1);\r
- DEBUG((DEBUG_BLKIO, "NorFlashPlatformInitialization: informational - Had to enable HSYS_FLASH flag.\n" ));\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-NorFlashPlatformGetDevices (\r
- OUT NOR_FLASH_DESCRIPTION **NorFlashDevices,\r
- OUT UINT32 *Count\r
- )\r
-{\r
- if ((NorFlashDevices == NULL) || (Count == NULL)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- *NorFlashDevices = mNorFlashDevices;\r
- *Count = sizeof (mNorFlashDevices) / sizeof (NOR_FLASH_DESCRIPTION);\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = NorFlashJunoLib\r
- FILE_GUID = 3eb6cbc4-ce95-11e2-b1bd-00241d0c1ba8\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = NorFlashPlatformLib\r
-\r
-[Sources.common]\r
- NorFlashJuno.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- DebugLib\r
- IoLib\r
projects / mirror_edk2.git / commitdiff